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[PATCH 13/22] target/arm: Remove fp_status_a64
From: |
Richard Henderson |
Subject: |
[PATCH 13/22] target/arm: Remove fp_status_a64 |
Date: |
Mon, 27 Jan 2025 15:25:55 -0800 |
Replace with fp_status[FPST_A64].
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 1 -
target/arm/cpu.c | 2 +-
target/arm/tcg/sme_helper.c | 2 +-
target/arm/tcg/vec_helper.c | 10 +++++-----
target/arm/vfp_helper.c | 16 ++++++++--------
5 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 06dbee5725..05a58de045 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -691,7 +691,6 @@ typedef struct CPUArchState {
float_status fp_status[FPST_COUNT];
struct {
float_status fp_status_a32;
- float_status fp_status_a64;
};
};
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ceb2dcb3fb..777e5f5dd8 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -551,7 +551,7 @@ static void arm_cpu_reset_hold(Object *obj, ResetType type)
set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
arm_set_default_fp_behaviours(&env->vfp.fp_status_a32);
- arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 6e336e10c6..dcc48e43db 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -1044,7 +1044,7 @@ void HELPER(sme_fmopa_h)(void *vza, void *vzn, void *vzm,
void *vpn,
* round-to-odd -- see above.
*/
fpst_f16 = env->vfp.fp_status[FPST_A64_F16];
- fpst_std = env->vfp.fp_status_a64;
+ fpst_std = env->vfp.fp_status[FPST_A64];
set_default_nan_mode(true, &fpst_std);
set_default_nan_mode(true, &fpst_f16);
fpst_odd = fpst_std;
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 61f268efad..9ed04b1b0a 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2184,7 +2184,7 @@ void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
- do_fmlal(vd, vn, vm, &env->vfp.fp_status_a64, desc,
+ do_fmlal(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc,
get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
}
@@ -2194,7 +2194,7 @@ void HELPER(sve2_fmlal_zzzw_s)(void *vd, void *vn, void
*vm, void *va,
intptr_t i, oprsz = simd_oprsz(desc);
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
- float_status *status = &env->vfp.fp_status_a64;
+ float_status *status = &env->vfp.fp_status[FPST_A64];
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
for (i = 0; i < oprsz; i += sizeof(float32)) {
@@ -2246,7 +2246,7 @@ void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void
*vm,
void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
- do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status_a64, desc,
+ do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status[FPST_A64], desc,
get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]));
}
@@ -2257,7 +2257,7 @@ void HELPER(sve2_fmlal_zzxw_s)(void *vd, void *vn, void
*vm, void *va,
uint16_t negn = extract32(desc, SIMD_DATA_SHIFT, 1) << 15;
intptr_t sel = extract32(desc, SIMD_DATA_SHIFT + 1, 1) * sizeof(float16);
intptr_t idx = extract32(desc, SIMD_DATA_SHIFT + 2, 3) * sizeof(float16);
- float_status *status = &env->vfp.fp_status_a64;
+ float_status *status = &env->vfp.fp_status[FPST_A64];
bool fz16 = get_flush_inputs_to_zero(&env->vfp.fp_status[FPST_A64_F16]);
for (i = 0; i < oprsz; i += 16) {
@@ -2936,7 +2936,7 @@ bool is_ebf(CPUARMState *env, float_status *statusp,
float_status *oddstatusp)
*/
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
- *statusp = env->vfp.fp_status_a64;
+ *statusp = env->vfp.fp_status[FPST_A64];
set_default_nan_mode(true, statusp);
if (ebf) {
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 6a6eb48530..e0d0623097 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -125,7 +125,7 @@ static uint32_t vfp_get_fpsr_from_host(CPUARMState *env)
a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16])
& ~float_flag_input_denormal_flushed);
- a64_flags |= get_float_exception_flags(&env->vfp.fp_status_a64);
+ a64_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A64]);
a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16])
& ~(float_flag_input_denormal_flushed |
float_flag_input_denormal_used));
/*
@@ -154,7 +154,7 @@ static void vfp_clear_float_status_exc_flags(CPUARMState
*env)
* be the architecturally up-to-date exception flag information first.
*/
set_float_exception_flags(0, &env->vfp.fp_status_a32);
- set_float_exception_flags(0, &env->vfp.fp_status_a64);
+ set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]);
set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]);
@@ -197,7 +197,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t
val, uint32_t mask)
break;
}
set_float_rounding_mode(i, &env->vfp.fp_status_a32);
- set_float_rounding_mode(i, &env->vfp.fp_status_a64);
+ set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]);
set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]);
}
@@ -215,7 +215,7 @@ static void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t
val, uint32_t mask)
if (changed & FPCR_FZ) {
bool ftz_enabled = val & FPCR_FZ;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
- set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_a64);
+ set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]);
/* FIZ is A64 only so FZ always makes A32 code flush inputs to zero */
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_a32);
}
@@ -226,12 +226,12 @@ static void vfp_set_fpcr_to_host(CPUARMState *env,
uint32_t val, uint32_t mask)
*/
bool fitz_enabled = (val & FPCR_FIZ) ||
(val & (FPCR_FZ | FPCR_AH)) == FPCR_FZ;
- set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status_a64);
+ set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A64]);
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a32);
- set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_a64);
+ set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]);
@@ -242,10 +242,10 @@ static void vfp_set_fpcr_to_host(CPUARMState *env,
uint32_t val, uint32_t mask)
if (ah_enabled) {
/* Change behaviours for A64 FP operations */
- arm_set_ah_fp_behaviours(&env->vfp.fp_status_a64);
+ arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
} else {
- arm_set_default_fp_behaviours(&env->vfp.fp_status_a64);
+ arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
}
}
--
2.43.0
- [PATCH 03/22] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16, (continued)
- [PATCH 03/22] target/arm: Rename FPST_FPCR_F16_A32 to FPST_A32_F16, Richard Henderson, 2025/01/27
- [PATCH 05/22] target/arm: Rename FPST_FPCR_AH* to FPST_AH*, Richard Henderson, 2025/01/27
- [PATCH 02/22] target/arm: Rename FPST_FPCR_A64 to FPST_A64, Richard Henderson, 2025/01/27
- [PATCH 07/22] target/arm: Remove standard_fp_status_f16, Richard Henderson, 2025/01/27
- [PATCH 16/22] target/arm: Simplify DO_VFP_cmp in vfp_helper.c, Richard Henderson, 2025/01/27
- [PATCH 18/22] target/arm: Introduce float*_maybe_ah_chs, Richard Henderson, 2025/01/27
- [PATCH 06/22] target/arm: Introduce CPUARMState.vfp.fp_status[], Richard Henderson, 2025/01/27
- [PATCH 04/22] target/arm: Rename FPST_FPCR_F16_A64 to FPST_A64_F16, Richard Henderson, 2025/01/27
- [PATCH 08/22] target/arm: Remove standard_fp_status, Richard Henderson, 2025/01/27
- [PATCH 09/22] target/arm: Remove ah_fp_status_f16, Richard Henderson, 2025/01/27
- [PATCH 13/22] target/arm: Remove fp_status_a64,
Richard Henderson <=
- [PATCH 15/22] target/arm: Simplify fp_status indexing in mve_helper.c, Richard Henderson, 2025/01/27
- [PATCH 12/22] target/arm: Remove fp_status_f16_a32, Richard Henderson, 2025/01/27
- [PATCH 14/22] target/arm: Remove fp_status_a32, Richard Henderson, 2025/01/27
- [PATCH 10/22] target/arm: Remove ah_fp_status, Richard Henderson, 2025/01/27
- [PATCH 11/22] target/arm: Remove fp_status_f16_a64, Richard Henderson, 2025/01/27
- [PATCH 19/22] target/arm: Use float*_maybe_ah_chs in sve_ftssel_*, Richard Henderson, 2025/01/27
- [PATCH 22/22] target/arm: Use flags for AH negation in do_fmla_zpzzz_*, Richard Henderson, 2025/01/27
- [PATCH 17/22] target/arm: Move float*_ah_chs to vec_internal.h, Richard Henderson, 2025/01/27
- [PATCH 21/22] target/arm: Use float*_maybe_ah_chs in sve_ftmad_*, Richard Henderson, 2025/01/27
- [PATCH 20/22] target/arm: Use float*_maybe_ah_chs in sve_ftmad_*, Richard Henderson, 2025/01/27