Make is_prefix_insn_excp() prototype but have it guarded by
a tcg_enabled() check. Inline part of it in powerpc_excp_books().
Extract POWERPC_EXCP_HV_EMU handling code to ppc_tcg_hv_emu(),
also exposing its prototype in "internal.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/ppc/internal.h | 3 ++
target/ppc/excp_helper.c | 101 +++++------------------------------
target/ppc/tcg-excp_helper.c | 71 ++++++++++++++++++++++++
3 files changed, 86 insertions(+), 89 deletions(-)
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
@@ -1310,7 +1236,15 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
}
vector |= env->excp_prefix;
- if (is_prefix_insn_excp(cpu, excp)) {
+ if (env->insns_flags2 & PPC2_ISA310) {
+ /* nothing to do */
+ } else if (kvm_enabled()) {
+ /*
+ * This does not load instructions and set the prefix bit correctly
+ * for injected interrupts with KVM. That may have to be discovered
+ * and set by the KVM layer before injecting.
+ */
+ } else if (tcg_enabled() && is_prefix_insn_excp(env, excp)) {
msr |= PPC_BIT(34);
}
@@ -1484,20 +1418,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
#ifdef CONFIG_TCG
- case POWERPC_EXCP_HV_EMU: {
- uint32_t insn = ppc_ldl_code(env, env->nip);
- env->spr[SPR_HEIR] = insn;
- if (is_prefix_insn(env, insn)) {
- uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
- env->spr[SPR_HEIR] <<= 32;
- env->spr[SPR_HEIR] |= insn2;
- }
- srr0 = SPR_HSRR0;
- srr1 = SPR_HSRR1;
- new_msr |= (target_ulong)MSR_HVB;
- new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+ case POWERPC_EXCP_HV_EMU:
+ ppc_tcg_hv_emu(env, &new_msr, &srr0, &srr1);
break;
- }
#endif
+void ppc_tcg_hv_emu(CPUPPCState *env, target_ulong *new_msr,
+ int *srr0, int *srr1)
+{
+ uint32_t insn = ppc_ldl_code(env, env->nip);
+
+ env->spr[SPR_HEIR] = insn;
+ if (is_prefix_insn(env, insn)) {
+ uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
+
+ env->spr[SPR_HEIR] <<= 32;
+ env->spr[SPR_HEIR] |= insn2;
+ }
+ *srr0 = SPR_HSRR0;
+ *srr1 = SPR_HSRR1;
+ *new_msr |= (target_ulong)MSR_HVB;
+ *new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
+}
+
#endif /* !CONFIG_USER_ONLY */