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[PATCH 48/76] target/arm: Implement FPCR.AH semantics for FMINP and FMAX
From: |
Peter Maydell |
Subject: |
[PATCH 48/76] target/arm: Implement FPCR.AH semantics for FMINP and FMAXP |
Date: |
Fri, 24 Jan 2025 16:28:08 +0000 |
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/helper-sve.h | 14 ++++++++++++++
target/arm/tcg/translate-a64.c | 25 +++++++++++++++++++++----
target/arm/tcg/vec_helper.c | 10 ++++++++++
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h
index f1b4606f763..8349752e99b 100644
--- a/target/arm/tcg/helper-sve.h
+++ b/target/arm/tcg/helper-sve.h
@@ -986,6 +986,20 @@ DEF_HELPER_FLAGS_5(gvec_ah_fmin_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(gvec_ah_fmin_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
+DEF_HELPER_FLAGS_5(gvec_ah_fmaxp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+DEF_HELPER_FLAGS_5(gvec_ah_fmaxp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+DEF_HELPER_FLAGS_5(gvec_ah_fmaxp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+
+DEF_HELPER_FLAGS_5(gvec_ah_fminp_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+DEF_HELPER_FLAGS_5(gvec_ah_fminp_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+DEF_HELPER_FLAGS_5(gvec_ah_fminp_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, fpst, i32)
+
DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index c07e22bad31..9d164b80c22 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -5776,14 +5776,24 @@ static gen_helper_gvec_3_ptr * const f_vector_fmaxp[3]
= {
gen_helper_gvec_fmaxp_s,
gen_helper_gvec_fmaxp_d,
};
-TRANS(FMAXP_v, do_fp3_vector, a, 0, f_vector_fmaxp)
+static gen_helper_gvec_3_ptr * const f_vector_ah_fmaxp[3] = {
+ gen_helper_gvec_ah_fmaxp_h,
+ gen_helper_gvec_ah_fmaxp_s,
+ gen_helper_gvec_ah_fmaxp_d,
+};
+TRANS(FMAXP_v, do_fp3_vector_2fn, a, 0, f_vector_fmaxp, f_vector_ah_fmaxp)
static gen_helper_gvec_3_ptr * const f_vector_fminp[3] = {
gen_helper_gvec_fminp_h,
gen_helper_gvec_fminp_s,
gen_helper_gvec_fminp_d,
};
-TRANS(FMINP_v, do_fp3_vector, a, 0, f_vector_fminp)
+static gen_helper_gvec_3_ptr * const f_vector_ah_fminp[3] = {
+ gen_helper_gvec_ah_fminp_h,
+ gen_helper_gvec_ah_fminp_s,
+ gen_helper_gvec_ah_fminp_d,
+};
+TRANS(FMINP_v, do_fp3_vector_2fn, a, 0, f_vector_fminp, f_vector_ah_fminp)
static gen_helper_gvec_3_ptr * const f_vector_fmaxnmp[3] = {
gen_helper_gvec_fmaxnump_h,
@@ -6775,9 +6785,16 @@ static bool do_fp3_scalar_pair(DisasContext *s, arg_rr_e
*a, const FPScalar *f)
return true;
}
+static bool do_fp3_scalar_pair_2fn(DisasContext *s, arg_rr_e *a,
+ const FPScalar *fnormal,
+ const FPScalar *fah)
+{
+ return do_fp3_scalar_pair(s, a, s->fpcr_ah ? fah : fnormal);
+}
+
TRANS(FADDP_s, do_fp3_scalar_pair, a, &f_scalar_fadd)
-TRANS(FMAXP_s, do_fp3_scalar_pair, a, &f_scalar_fmax)
-TRANS(FMINP_s, do_fp3_scalar_pair, a, &f_scalar_fmin)
+TRANS(FMAXP_s, do_fp3_scalar_pair_2fn, a, &f_scalar_fmax, &f_scalar_fmax_ah)
+TRANS(FMINP_s, do_fp3_scalar_pair_2fn, a, &f_scalar_fmin, &f_scalar_fmin_ah)
TRANS(FMAXNMP_s, do_fp3_scalar_pair, a, &f_scalar_fmaxnm)
TRANS(FMINNMP_s, do_fp3_scalar_pair, a, &f_scalar_fminnm)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index c7af9a04a27..d3f2eaa807e 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2444,6 +2444,16 @@ DO_3OP_PAIR(gvec_fminnump_h, float16_minnum, float16, H2)
DO_3OP_PAIR(gvec_fminnump_s, float32_minnum, float32, H4)
DO_3OP_PAIR(gvec_fminnump_d, float64_minnum, float64, )
+#ifdef TARGET_AARCH64
+DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2)
+DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4)
+DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, )
+
+DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2)
+DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4)
+DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, )
+#endif
+
#undef DO_3OP_PAIR
#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \
--
2.34.1
- [PATCH 63/76] target/arm: Handle FPCR.AH in negation step in FMLS (indexed), (continued)
- [PATCH 63/76] target/arm: Handle FPCR.AH in negation step in FMLS (indexed), Peter Maydell, 2025/01/24
- [PATCH 74/76] target/i386: Use correct type for get_float_exception_flags() values, Peter Maydell, 2025/01/24
- [PATCH 76/76] tests/tcg/x86_64/fma: add test for exact-denormal output, Peter Maydell, 2025/01/24
- [PATCH 41/76] target/arm: Handle FPCR.NEP in do_cvtf_scalar(), Peter Maydell, 2025/01/24
- [PATCH 43/76] target/arm: Handle FPCR.NEP for FCVTXN (scalar), Peter Maydell, 2025/01/24
- [PATCH 44/76] target/arm: Handle FPCR.NEP for NEP for FMUL, FMULX scalar by element, Peter Maydell, 2025/01/24
- [PATCH 48/76] target/arm: Implement FPCR.AH semantics for FMINP and FMAXP,
Peter Maydell <=
- [PATCH 53/76] target/arm: Implement FPCR.AH handling for scalar FABS and FABD, Peter Maydell, 2025/01/24
- [PATCH 51/76] target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX vector, Peter Maydell, 2025/01/24
- [PATCH 56/76] target/arm: Handle FPCR.AH in SVE FABS, Peter Maydell, 2025/01/24
- [PATCH 59/76] target/arm: Handle FPCR.AH in negation steps in SVE FCADD, Peter Maydell, 2025/01/24
- [PATCH 71/76] target/arm: Implement increased precision FRSQRTE, Peter Maydell, 2025/01/24