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[PATCH 75/76] target/i386: Wire up MXCSR.DE and FPUS.DE correctly
From: |
Peter Maydell |
Subject: |
[PATCH 75/76] target/i386: Wire up MXCSR.DE and FPUS.DE correctly |
Date: |
Fri, 24 Jan 2025 16:28:35 +0000 |
The x86 DE bit in the FPU and MXCSR status is supposed to be set
when an input denormal is consumed. We didn't previously report
this from softfloat, so the x86 code either simply didn't set
the DE bit or else incorrectly wired it up to denormal_flushed,
depending on which register you looked at.
Now we have input_denormal_used we can wire up these DE bits
with the semantics they are supposed to have.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/i386/tcg/fpu_helper.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 97b46307d56..fd1cd823e9e 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -215,7 +215,7 @@ static void merge_exception_flags(CPUX86State *env, int
old_flags)
(new_flags & float_flag_overflow ? FPUS_OE : 0) |
(new_flags & float_flag_underflow ? FPUS_UE : 0) |
(new_flags & float_flag_inexact ? FPUS_PE : 0) |
- (new_flags & float_flag_input_denormal_flushed ?
FPUS_DE : 0)));
+ (new_flags & float_flag_input_denormal_used ? FPUS_DE :
0)));
}
static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
@@ -3251,6 +3251,7 @@ void update_mxcsr_status(CPUX86State *env)
/* Set exception flags. */
set_float_exception_flags((mxcsr & FPUS_IE ? float_flag_invalid : 0) |
+ (mxcsr & FPUS_DE ?
float_flag_input_denormal_used : 0) |
(mxcsr & FPUS_ZE ? float_flag_divbyzero : 0) |
(mxcsr & FPUS_OE ? float_flag_overflow : 0) |
(mxcsr & FPUS_UE ? float_flag_underflow : 0) |
@@ -3267,14 +3268,8 @@ void update_mxcsr_status(CPUX86State *env)
void update_mxcsr_from_sse_status(CPUX86State *env)
{
int flags = get_float_exception_flags(&env->sse_status);
- /*
- * The MXCSR denormal flag has opposite semantics to
- * float_flag_input_denormal_flushed (the softfloat code sets that flag
- * only when flushing input denormals to zero, but SSE sets it
- * only when not flushing them to zero), so is not converted
- * here.
- */
env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
+ (flags & float_flag_input_denormal_used ? FPUS_DE : 0) |
(flags & float_flag_divbyzero ? FPUS_ZE : 0) |
(flags & float_flag_overflow ? FPUS_OE : 0) |
(flags & float_flag_underflow ? FPUS_UE : 0) |
--
2.34.1
- [PATCH 40/76] target/arm: Handle FPCR.NEP for 1-input scalar operations, (continued)
- [PATCH 40/76] target/arm: Handle FPCR.NEP for 1-input scalar operations, Peter Maydell, 2025/01/24
- [PATCH 68/76] target/arm: Enable FEAT_AFP for '-cpu max', Peter Maydell, 2025/01/24
- [PATCH 69/76] target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper, Peter Maydell, 2025/01/24
- [PATCH 47/76] target/arm: Implement FPCR.AH semantics for FMAXV and FMINV, Peter Maydell, 2025/01/24
- [PATCH 49/76] target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV, Peter Maydell, 2025/01/24
- [PATCH 75/76] target/i386: Wire up MXCSR.DE and FPUS.DE correctly,
Peter Maydell <=
- [PATCH 52/76] target/arm: Implement FPCR.AH handling of negation of NaN, Peter Maydell, 2025/01/24
- [PATCH 54/76] target/arm: Handle FPCR.AH in vector FABD, Peter Maydell, 2025/01/24
- [PATCH 57/76] target/arm: Handle FPCR.AH in SVE FABD, Peter Maydell, 2025/01/24
- [PATCH 58/76] target/arm: Handle FPCR.AH in negation steps in FCADD, Peter Maydell, 2025/01/24
- [PATCH 60/76] target/arm: Handle FPCR.AH in FMLSL, Peter Maydell, 2025/01/24