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[PATCH 73/76] target/i386: Detect flush-to-zero after rounding
From: |
Peter Maydell |
Subject: |
[PATCH 73/76] target/i386: Detect flush-to-zero after rounding |
Date: |
Fri, 24 Jan 2025 16:28:33 +0000 |
The Intel SDM section 10.2.3.3 on the MXCSR.FTZ bit says that we
flush outputs to zero when we detect underflow, which is after
rounding. Set the detect_ftz flag accordingly.
This allows us to enable the test in fma.c which checks this
behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/i386/tcg/fpu_helper.c | 8 ++++----
tests/tcg/x86_64/fma.c | 5 -----
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 9bf23fdd0f6..5c233fdf5b4 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -189,13 +189,13 @@ void cpu_init_fp_statuses(CPUX86State *env)
set_float_default_nan_pattern(0b11000000, &env->mmx_status);
set_float_default_nan_pattern(0b11000000, &env->sse_status);
/*
- * TODO: x86 does flush-to-zero detection after rounding (the SDM
+ * x86 does flush-to-zero detection after rounding (the SDM
* section 10.2.3.3 on the FTZ bit of MXCSR says that we flush
* when we detect underflow, which x86 does after rounding).
*/
- set_float_detect_ftz(detect_ftz_before_rounding, &env->fp_status);
- set_float_detect_ftz(detect_ftz_before_rounding, &env->mmx_status);
- set_float_detect_ftz(detect_ftz_before_rounding, &env->sse_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->fp_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->mmx_status);
+ set_float_detect_ftz(detect_ftz_after_rounding, &env->sse_status);
}
static inline uint8_t save_exception_flags(CPUX86State *env)
diff --git a/tests/tcg/x86_64/fma.c b/tests/tcg/x86_64/fma.c
index 09c622ebc00..46f863005ed 100644
--- a/tests/tcg/x86_64/fma.c
+++ b/tests/tcg/x86_64/fma.c
@@ -79,14 +79,9 @@ static testdata tests[] = {
/*
* Flushing of denormal outputs to zero should also happen after
* rounding, so setting FTZ should not affect the result or the flags.
- * QEMU currently does not emulate this correctly because we do the
- * flush-to-zero check before rounding, so we incorrectly produce a
- * zero result and set Underflow as well as Precision.
*/
-#ifdef ENABLE_FAILING_TESTS
{ 0x3fdfffffffffffff, 0x001fffffffffffff, 0x801fffffffffffff, true,
0x8010000000000000, 0x20 }, /* Enabling FTZ shouldn't change flags */
-#endif
};
int main(void)
--
2.34.1
- [PATCH 66/76] target/arm: Handle FPCR.AH in SVE FTSSEL, (continued)
- [PATCH 66/76] target/arm: Handle FPCR.AH in SVE FTSSEL, Peter Maydell, 2025/01/24
- [PATCH 34/76] target/arm: Use FPST_FPCR_AH for BFCVT* insns, Peter Maydell, 2025/01/24
- [PATCH 37/76] target/arm: Define and use new write_fp_*reg_merging() functions, Peter Maydell, 2025/01/24
- [PATCH 62/76] target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insns, Peter Maydell, 2025/01/24
- [PATCH 38/76] target/arm: Handle FPCR.NEP for 3-input scalar operations, Peter Maydell, 2025/01/24
- [PATCH 73/76] target/i386: Detect flush-to-zero after rounding,
Peter Maydell <=
- [PATCH 39/76] target/arm: Handle FPCR.NEP for BFCVT scalar, Peter Maydell, 2025/01/24
- [PATCH 40/76] target/arm: Handle FPCR.NEP for 1-input scalar operations, Peter Maydell, 2025/01/24
- [PATCH 68/76] target/arm: Enable FEAT_AFP for '-cpu max', Peter Maydell, 2025/01/24
- [PATCH 69/76] target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper, Peter Maydell, 2025/01/24
- [PATCH 47/76] target/arm: Implement FPCR.AH semantics for FMAXV and FMINV, Peter Maydell, 2025/01/24