Re: [PATCH] target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0

[Daniel Henrique Barboza]

On 1/24/25 7:14 AM, Max Chou wrote:
> According to the Vector Reduction Operations section in the RISC-V "V"
> Vector Extension spec,
> "If vl=0, no operation is performed and the destination register is not
> updated."
>
> The vd should be updated when vl is larger than 0.

Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction 
instructions")
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")

> Signed-off-by: Max Chou <max.chou@sifive.com>

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

> ---
>   target/riscv/vector_helper.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 5386e3b97c5..7773df6a7c7 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4659,7 +4659,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          
> \
>           }                                                 \
>           s1 = OP(s1, (TD)s2);                              \
>       }                                                     \
> -    *((TD *)vd + HD(0)) = s1;                             \
> +    if (vl > 0) {                                         \
> +        *((TD *)vd + HD(0)) = s1;                         \
> +    }                                                     \
>       env->vstart = 0;                                      \
>       /* set tail elements to 1s */                         \
>       vext_set_elems_1s(vd, vta, esz, vlenb);               \
> @@ -4745,7 +4747,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,          
>  \
>           }                                                  \
>           s1 = OP(s1, (TD)s2, &env->fp_status);              \
>       }                                                      \
> -    *((TD *)vd + HD(0)) = s1;                              \
> +    if (vl > 0) {                                          \
> +        *((TD *)vd + HD(0)) = s1;                          \
> +    }                                                      \
>       env->vstart = 0;                                       \
>       /* set tail elements to 1s */                          \
>       vext_set_elems_1s(vd, vta, esz, vlenb);                \