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[PULL v2 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch
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From: |
Alistair Francis |
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Subject: |
[PULL v2 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch |
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Date: |
Sun, 19 Jan 2025 11:12:18 +1000 |
From: Clément Léger <cleger@rivosinc.com>
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-6-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5540eb7f63..9e1ce0e1f1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -205,6 +205,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
+ ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp),
ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
@@ -1628,6 +1629,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
+ MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false),
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
--
2.48.1
- [PULL v2 36/50] target/riscv: Invoke pmu init after feature enable, (continued)
- [PULL v2 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/18
- [PULL v2 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/18
- [PULL v2 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/18
- [PULL v2 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/18
- [PULL v2 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/18
- [PULL v2 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/18
- [PULL v2 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/18
- [PULL v2 44/50] target/riscv: Add Smdbltrp CSRs handling, Alistair Francis, 2025/01/18
- [PULL v2 45/50] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/18
- [PULL v2 47/50] target/riscv: Add Smdbltrp ISA extension enable switch, Alistair Francis, 2025/01/18
- [PULL v2 43/50] target/riscv: Add Ssdbltrp ISA extension enable switch,
Alistair Francis <=
- [PULL v2 46/50] target/riscv: Implement Smdbltrp behavior, Alistair Francis, 2025/01/18
- [PULL v2 49/50] target/riscv: Support Supm and Sspm as part of Zjpm v1.0, Alistair Francis, 2025/01/18
- [PULL v2 48/50] hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache, Alistair Francis, 2025/01/18
- [PULL v2 50/50] hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events, Alistair Francis, 2025/01/18