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[PULL v2 32/50] target/riscv: Add properties for counter delegation ISA
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From: |
Alistair Francis |
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Subject: |
[PULL v2 32/50] target/riscv: Add properties for counter delegation ISA extensions |
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Date: |
Sun, 19 Jan 2025 11:12:07 +1000 |
From: Atish Patra <atishp@rivosinc.com>
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-5-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 2 ++
target/riscv/cpu.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 4fe2144ec7..561f5119b6 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -78,6 +78,8 @@ struct RISCVCPUConfig {
bool ext_ztso;
bool ext_smstateen;
bool ext_sstc;
+ bool ext_smcdeleg;
+ bool ext_ssccfg;
bool ext_smcntrpmf;
bool ext_smcsrind;
bool ext_sscsrind;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4f5772ae5b..da40f68715 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
+ ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
@@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_13_0, ext_smnpm),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
+ ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_13_0, ext_ssccfg),
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
--
2.48.1
- [PULL v2 22/50] target/riscv: Handle Smrnmi interrupt and exception, (continued)
- [PULL v2 22/50] target/riscv: Handle Smrnmi interrupt and exception, Alistair Francis, 2025/01/18
- [PULL v2 23/50] target/riscv: Add Smrnmi mnret instruction, Alistair Francis, 2025/01/18
- [PULL v2 24/50] target/riscv: Add Smrnmi cpu extension, Alistair Francis, 2025/01/18
- [PULL v2 25/50] target/riscv: Add Zicfilp support for Smrnmi, Alistair Francis, 2025/01/18
- [PULL v2 26/50] target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu, Alistair Francis, 2025/01/18
- [PULL v2 27/50] hw/riscv/virt: Remove unnecessary use of &first_cpu, Alistair Francis, 2025/01/18
- [PULL v2 28/50] target/riscv: Add properties for Indirect CSR Access extension, Alistair Francis, 2025/01/18
- [PULL v2 29/50] target/riscv: Decouple AIA processing from xiselect and xireg, Alistair Francis, 2025/01/18
- [PULL v2 30/50] target/riscv: Enable S*stateen bits for AIA, Alistair Francis, 2025/01/18
- [PULL v2 31/50] target/riscv: Support generic CSR indirect access, Alistair Francis, 2025/01/18
- [PULL v2 32/50] target/riscv: Add properties for counter delegation ISA extensions,
Alistair Francis <=
- [PULL v2 33/50] target/riscv: Add counter delegation definitions, Alistair Francis, 2025/01/18
- [PULL v2 34/50] target/riscv: Add select value range check for counter delegation, Alistair Francis, 2025/01/18
- [PULL v2 35/50] target/riscv: Add counter delegation/configuration support, Alistair Francis, 2025/01/18
- [PULL v2 36/50] target/riscv: Invoke pmu init after feature enable, Alistair Francis, 2025/01/18
- [PULL v2 37/50] target/riscv: Add implied rule for counter delegation extensions, Alistair Francis, 2025/01/18
- [PULL v2 38/50] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg, Alistair Francis, 2025/01/18
- [PULL v2 41/50] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Alistair Francis, 2025/01/18
- [PULL v2 40/50] target/riscv: Add Ssdbltrp CSRs handling, Alistair Francis, 2025/01/18
- [PULL v2 39/50] target/riscv: Fix henvcfg potentially containing stale bits, Alistair Francis, 2025/01/18
- [PULL v2 42/50] target/riscv: Implement Ssdbltrp exception handling, Alistair Francis, 2025/01/18