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[PULL v2 09/50] target/riscv: add shgatpa
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From: |
Alistair Francis |
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Subject: |
[PULL v2 09/50] target/riscv: add shgatpa |
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Date: |
Sun, 19 Jan 2025 11:11:44 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
shgatpa is defined in RVA22 as:
"For each supported virtual memory scheme SvNN supported in satp, the
corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare
must also be supported."
Claim support for shgatpa since this is always true for TCG.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241218114026.1652352-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 382 -> 390 bytes
2 files changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2f58eeb689..3e138572d4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(shvstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
diff --git a/tests/data/acpi/riscv64/virt/RHCT
b/tests/data/acpi/riscv64/virt/RHCT
index fcd9c95a6a..695022d56c 100644
Binary files a/tests/data/acpi/riscv64/virt/RHCT and
b/tests/data/acpi/riscv64/virt/RHCT differ
--
2.48.1
- [PULL v2 00/50] riscv-to-apply queue, Alistair Francis, 2025/01/18
- [PULL v2 01/50] target/riscv: rvv: fix typo in vext continuous ldst function names, Alistair Francis, 2025/01/18
- [PULL v2 02/50] target/riscv: rvv: speed up small unit-stride loads and stores, Alistair Francis, 2025/01/18
- [PULL v2 03/50] riscv/gdbstub: add V bit to priv reg, Alistair Francis, 2025/01/18
- [PULL v2 04/50] target/riscv: add shcounterenw, Alistair Francis, 2025/01/18
- [PULL v2 05/50] target/riscv: add shvstvala, Alistair Francis, 2025/01/18
- [PULL v2 06/50] target/riscv: add shtvala, Alistair Francis, 2025/01/18
- [PULL v2 07/50] target/riscv: add shvstvecd, Alistair Francis, 2025/01/18
- [PULL v2 08/50] target/riscv: add shvsatpa, Alistair Francis, 2025/01/18
- [PULL v2 09/50] target/riscv: add shgatpa,
Alistair Francis <=
- [PULL v2 10/50] target/riscv/tcg: add sha, Alistair Francis, 2025/01/18
- [PULL v2 11/50] target/riscv: use RISCVException enum in exception helpers, Alistair Francis, 2025/01/18
- [PULL v2 12/50] target/riscv: add trace in riscv_raise_exception(), Alistair Francis, 2025/01/18
- [PULL v2 13/50] target/riscv: Remove obsolete pointer masking extension code., Alistair Francis, 2025/01/18
- [PULL v2 14/50] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, Alistair Francis, 2025/01/18
- [PULL v2 15/50] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, Alistair Francis, 2025/01/18
- [PULL v2 16/50] target/riscv: Add pointer masking tb flags, Alistair Francis, 2025/01/18
- [PULL v2 17/50] target/riscv: Update address modify functions to take into account pointer masking, Alistair Francis, 2025/01/18
- [PULL v2 18/50] target/riscv: Apply pointer masking for virtualized memory accesses, Alistair Francis, 2025/01/18
- [PULL v2 19/50] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension, Alistair Francis, 2025/01/18