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| From: | Daniel Henrique Barboza |
| Subject: | Re: [PATCH 2/4] target/riscv: use RVB in RVA22U64 |
| Date: | Tue, 14 Jan 2025 13:08:46 -0300 |
| User-agent: | Mozilla Thunderbird |
On 1/14/25 11:52 AM, Andrew Jones wrote:
On Tue, Jan 14, 2025 at 10:20:10AM -0300, Daniel Henrique Barboza wrote:From the time we added RVA22U64 until now the spec didn't declare 'RVB' as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec [1] added the following in the 'RVA22U64 Mandatory Extensions' section: "B Bit-manipulation instructions Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the time of RVA22U64's ratification, the B extension had not yet been defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead. Mandating B is equivalent." It is also equivalent to QEMU (see riscv_cpu_validate_b() in target/riscv/tcg/tcg-cpu.c). Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension, not citing zba/zbb/zbs. To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a parent of RVA23), use RVB in RVA22U64 as well. As a bonus we can also exclude zba/zbb/zbs from 'ext_offsets' and make it a bit shorter. (bios-tables-test change: zba/zbb/zbs no longer on riscv,isa)We should still have zba/zbb/zbs on the ISA string. I don't think Linux yet supports expanding a 'B' bundle into them and other SW may also have not really cared about 'B' being designed to represent preexisting extensions after having already learned how to detect those extensions.
This has to do with how bios-tables-test works. The test doesn't boot the CPU up to realize() and finalize() and, with this change, we ended up removing zba/zbb/zbs from it because we won't reach riscv_cpu_validate_b() to add them back. I guess that in the end, aside from having a smaller ext list, there's not much to gain from removing zba/zbb/zbs from the profile definition. We can just add RVB and keep them. Thanks, Daniel
Anyway, what keeps them from being added? I don't see QEMU code for that. I do expect a bios tables change though, since the ISA string should now have 'B' added to it. Thanks, drew[1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 5 ++--- tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b187ef2e4b..8d0563527f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2351,13 +2351,12 @@ static const PropertyInfo prop_marchid = { static RISCVCPUProfile RVA22U64 = { .parent = NULL, .name = "rva22u64", - .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU, .priv_spec = RISCV_PROFILE_ATTR_UNUSED, .satp_mode = RISCV_PROFILE_ATTR_UNUSED, .ext_offsets = { CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), - CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), - CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin), + CPU_CFG_OFFSET(ext_zfhmin), CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr), CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom), CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz), diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644 GIT binary patch delta 53 zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S I3K$s}0ARKZK>z>% delta 52 zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF HMg|4|IwT82 -- 2.47.1
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