[PATCH 5/5] target/loongarch: Dump all generic CSR registers

[Bibo Mao]

CSR registers is import system control registers, it had better
dump all CSR registers when VM is running in system mode.

Here is dump output example of CSR registers:
 CSR000: CRMD b4 PRMD 4 EUEN 0 MISC 0
 CSR004: ECFG 71c3d ESTAT 0 ERA 9000000002e214c0 BADV 7ffff361401c
 CSR008: BADI 2b0000
 CSR012: EENTRY 9000000005680000
 CSR016: TLBIDX e0003c2 TLBEHI 7ffff3610000 TLBELO0 0 TLBELO1 40000001111d801f
 CSR024: ASID a00ce PGDL 9000000105f1c000 PGDH 9000000005650000 PGD 0
 CSR028: PWCL 5e56e PWCH 2e4 STLBPS e RVACFG 0
 CSR032: CPUID 0 PRCFG1 72f8 PRCFG2 3ffff000 PRCFG3 8073f2
 CSR048: SAVE0 0 SAVE1 1b504 SAVE2 7ffff34487a8 SAVE3 5e24000
 CSR052: SAVE4 0 SAVE5 0 SAVE6 0 SAVE7 0
 CSR056: SAVE8 0 SAVE9 0 SAVE10 0 SAVE11 0
 CSR060: SAVE12 0 SAVE13 0 SAVE14 0 SAVE15 0
 CSR064: TID 0 TCFG 50b06f5 TVAL 20ab7cf CNTC ffffffffce390f8f
 CSR068: TICLR 0
 CSR096: LLBCTL 1
 CSR128: IMPCTL1 0 IMPCTL2 0
 CSR136: TLBRENTRY 568a000 TLBRBADV ffff8000021143f8 TLBRERA 9000000003999930 
TLBRSAVE 9000000101684a00
 CSR140: TLBRELO0 40 TLBRELO1 10942c053 TLBREHI ffff80000211400e TLBRPRMD 4
 CSR144: MERRCTL 0 MERRINFO1 0 MERRINFO2 0 MERRENTRY 0
 CSR148: MERRERA 0 MERRSAVE 0
 CSR152: CTAG 0
 CSR384: DMW0 8000000000000001 DMW1 9000000000000011 DMW2 a000000000000021 DMW3 0

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
---
 target/loongarch/cpu.c | 58 +++++++++++++++++++++++++++++-------------
 target/loongarch/csr.c |  2 ++
 target/loongarch/csr.h |  1 +
 3 files changed, 44 insertions(+), 17 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d611a60470..31ef82cfe8 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -19,7 +19,7 @@
 #include "cpu.h"
 #include "internals.h"
 #include "fpu/softfloat-helpers.h"
-#include "cpu-csr.h"
+#include "csr.h"
 #ifndef CONFIG_USER_ONLY
 #include "system/reset.h"
 #endif
@@ -765,6 +765,44 @@ static ObjectClass *loongarch_cpu_class_by_name(const char 
*cpu_model)
     return oc;
 }
 
+static void loongarch_cpu_dump_csr(CPUState *cs, FILE *f)
+{
+#ifndef CONFIG_USER_ONLY
+    int i;
+    CSRInfo *csr_info;
+    CPULoongArchState *env = cpu_env(cs);
+    unsigned long *addr;
+    int col = 0;
+
+    qemu_fprintf(f, "\n");
+
+    /* Dump all generic CSR register */
+    for (i = 0; i < LOONGARCH_CSR_DBG; i++) {
+        csr_info = get_csr(i);
+        if (!csr_info) {
+            if (i == (col + 3)) {
+                qemu_fprintf(f, "\n");
+            }
+
+            continue;
+        }
+
+        if ((i >  (col + 3)) || (i == col)) {
+            col = i & ~3;
+            qemu_fprintf(f, " CSR%03d:", col);
+        }
+
+        addr = (void *)env + csr_info->offset;
+        qemu_fprintf(f, " %s %" PRIx64, csr_info->name, *addr);
+
+        if (i == (col + 3)) {
+            qemu_fprintf(f, "\n");
+        }
+    }
+    qemu_fprintf(f, "\n");
+#endif
+}
+
 static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
     CPULoongArchState *env = cpu_env(cs);
@@ -784,22 +822,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE 
*f, int flags)
         }
     }
 
-    qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
-    qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
-    qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
-    qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
-    qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
-    qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
-    qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
-    qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
-    qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
-                 " PRCFG3=%016" PRIx64 "\n",
-                 env->CSR_PRCFG1, env->CSR_PRCFG2, env->CSR_PRCFG3);
-    qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
-    qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
-    qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
-    qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
-    qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
+    /* csr */
+    loongarch_cpu_dump_csr(cs, f);
 
     /* fpr */
     if (flags & CPU_DUMP_FPU) {
diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c
index 62c1815bfb..8ad6448c69 100644
--- a/target/loongarch/csr.c
+++ b/target/loongarch/csr.c
@@ -9,12 +9,14 @@
 
 #define CSR_OFF_FUNCS(NAME, FL, RD, WR)                    \
     [LOONGARCH_CSR_##NAME] = {                             \
+        .name   = (stringify(NAME)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME), \
         .flags = FL, .readfn = RD, .writefn = WR           \
     }
 
 #define CSR_OFF_ARRAY(NAME, N)                                \
     [LOONGARCH_CSR_##NAME(N)] = {                             \
+        .name   = (stringify(NAME##N)),                       \
         .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
         .flags = 0, .readfn = NULL, .writefn = NULL           \
     }
diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h
index d32a607975..fba48258c8 100644
--- a/target/loongarch/csr.h
+++ b/target/loongarch/csr.h
@@ -26,6 +26,7 @@ enum {
 };
 
 typedef struct {
+    const char *name;
     int offset;
     int flags;
     GenCSRRead readfn;
-- 
2.39.3