Re: [PATCH v7 1/5] hw/core/machine: Reject thread level cache

[Zhao Liu]

Hi Jonathon,

Thanks for more explaination!

Based on your clarification, I think the commit message for Patch 1
needs to be updated since I used the same wrods as the cover letter...

What about the following change?

On Wed, Jan 08, 2025 at 11:01:46PM +0800, Zhao Liu wrote:
> Date: Wed, 8 Jan 2025 23:01:46 +0800
> From: Zhao Liu <zhao1.liu@intel.com>
> Subject: [PATCH v7 1/5] hw/core/machine: Reject thread level cache
> X-Mailer: git-send-email 2.34.1
> 
> Currently, neither i386 nor ARM have real hardware support for per-
> thread cache, and there is no clear demand for this specific cache
> topology.
> 
> Additionally, since supporting this special cache topology on ARM
> requires extra effort [1], it is unnecessary to support it at this
> moment, even though per-thread cache might have potential scheduling
> benefits for VMs without CPU affinity.

Additionally, since ARM even can't support this special cache topology
in device tree, it is unnecessary to support it at this moment, even
though per-thread cache might have potential scheduling benefits for
VMs without CPU affinity.

If it's fine for u, I'll resend this series quickly.

Thanks,
Zhao

> Therefore, disable thread-level cache topology in the general machine
> part. At present, i386 has not enabled SMP cache, so disabling the
> thread parameter does not pose compatibility issues.
> 
> In the future, if there is a clear demand for this feature, the correct
> approach would be to add a new control field in MachineClass.smp_props
> and enable it only for the machines that require it.
> 
> [1]: Z3efFsigJ6SxhqMf@intel.com/#t">https://lore.kernel.org/qemu-devel/Z3efFsigJ6SxhqMf@intel.com/#t
> 
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>