Re: [PATCH v4 00/11] Add RISC-V Counter delegation ISA extension support

[Alistair Francis]

On Wed, Dec 4, 2024 at 9:18 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> This series adds the counter delegation extension support. The counter
> delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
> extensions.
>
> 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
>    5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of
>    RISC-V CSR address space.
> 2. Smstateen: The stateen bit[60] controls the access to the registers
>    indirectly via the above indirect registers.
> 3. Smcdeleg/Ssccfg: The counter delegation extensions[2]
>
> The counter delegation extension allows Supervisor mode to program the
> hpmevent and hpmcounters directly without needing the assistance from the
> M-mode via SBI calls. This results in a faster perf profiling and very
> few traps. This extension also introduces a scountinhibit CSR which allows
> to stop/start any counter directly from the S-mode. As the counter
> delegation extension potentially can have more than 100 CSRs, the 
> specificaiton
> leverages the indirect CSR extension to save the precious CSR address range.
>
> Due to the dependancy of these extensions, the following extensions must be
> enabled to use the counter delegation feature in S-mode.
>
> "smstateen=true,sscofpmf=true,ssccfg=true,smcdeleg=true,smcsrind=true,sscsrind=true"
>
> This makes the qemu command line quite tedious. The previous version, I tried
> to introduce a preferred rule to enable all but it was decided that an user
> should opt to use max cpu if they don't want to enable all the dependant ISA
> extensions by hand. This series got rid of the preferred rule and added 2
> patches for specifiying the mandatory ISA extensions via implied rule.
>
> The first 2 patches decouple the indirect CSR usage from AIA implementation
> while patch3 adds stateen bits validation for AIA.
> The PATCH4 implements indirect CSR extensions while remaining patches
> implement the counter delegation extensions.
>
> The Qemu patches can be found here:
> https://github.com/atishp04/qemu/tree/b4/counter_delegation_v4
> The Linux kernel patches can be found here (WIP version due to onging upstream
> dependant patches):
> https://github.com/atishp04/linux/tree/b4/counter_delegation_v2
>
> [1] https://github.com/riscv/riscv-indirect-csr-access
> [2] https://github.com/riscv/riscv-smcdeleg-ssccfg
>
> Cc: kaiwenxue1@gmail.com
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Changes in v4:
> - Fixed the comments recieved on v3.
> - code style comments and removed 1 redundant if else block.
> - Link to v3: 
> https://lore.kernel.org/r/20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com
>
> Changes in v3:
> 1. Updated the priv version in extensions
> 2. Fixed minor issues pointed out in v2.
> 3. Dropped preferred rule and added an implied rule for AIA and counter
>    delegation.
> - Link to v2: 
> https://lore.kernel.org/r/20240723-counter_delegation-v2-0-c4170a5348ca@rivosinc.com
>
> Changes from previous RFC version:
>
> 1. Renamed sxcsrind to csrind to align with other function names.
> 2. Enable sscofpmf by default for virt machine.
> 3. Introduced a preferred extension enabling rule strategy for generic
> mult-extension dependencies.
> 4. Enables all PMU related extensions if ssccfg extension is set.
>
> RFC Link:
> https://lore.kernel.org/all/35a4d40c-9d0d-4a0a-a2c9-5d5f7def9b9c@ventanamicro.com/T/
>
> ---
> Atish Patra (5):
>       target/riscv: Enable S*stateen bits for AIA
>       target/riscv: Add properties for counter delegation ISA extensions
>       target/riscv: Invoke pmu init after feature enable
>       target/riscv: Add implied rule for counter delegation extensions
>       target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
>
> Kaiwen Xue (6):
>       target/riscv: Add properties for Indirect CSR Access extension
>       target/riscv: Decouple AIA processing from xiselect and xireg
>       target/riscv: Support generic CSR indirect access
>       target/riscv: Add counter delegation definitions
>       target/riscv: Add select value range check for counter delegation
>       target/riscv: Add counter delegation/configuration support
>
>  target/riscv/cpu.c         |  20 +-
>  target/riscv/cpu.h         |   1 +
>  target/riscv/cpu_bits.h    |  34 ++-
>  target/riscv/cpu_cfg.h     |   4 +
>  target/riscv/csr.c         | 718 
> ++++++++++++++++++++++++++++++++++++++++++---
>  target/riscv/machine.c     |   1 +
>  target/riscv/tcg/tcg-cpu.c |  28 +-
>  7 files changed, 753 insertions(+), 53 deletions(-)

This has all been Acked now, do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next ?

Alistair

> ---
> base-commit: 27652f9ca9d831c67dd447346c6ee953669255f0
> change-id: 20240715-counter_delegation-10ab44c7d2c0
> --
> Regards,
> Atish patra
>
>