[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v9 0/8] Support RISC-V IOPMP
From: |
Ethan Chen |
Subject: |
[PATCH v9 0/8] Support RISC-V IOPMP |
Date: |
Thu, 9 Jan 2025 10:44:33 +0800 |
When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.
The issue of CPU access to non-CPU address space via IOMMU was previously
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
this patch.
You can use a customized QEMU[2] to run bare-metal demo[3] to show IOPMP
functionality. The modifications involve applying patch[1] and adding a simple
DMA device along with a second IOPMP device to the virt machine. These
additional devices are intended to demonstrate more complex scenarios for IOPMP.
[1] accel/tcg: Store section pointer in CPUTLBEntryFull
https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/
[2] https://github.com/zhanyangch/qemu/tree/iopmp_patch_v9_test
[3] https://github.com/zhanyangch/iopmp-test
Ethan Chen (8):
hw/core: Add config stream
memory: Introduce memory region fetch operation
system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
size
target/riscv: Add support for IOPMP
hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
hw/misc/riscv_iopmp: Add RISC-V IOPMP device
hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction
infomation
hw/riscv/virt: Add IOPMP support
accel/tcg/cputlb.c | 29 +-
docs/system/riscv/virt.rst | 7 +
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +
hw/core/meson.build | 2 +-
hw/misc/Kconfig | 4 +
hw/misc/meson.build | 2 +
hw/misc/riscv_iopmp.c | 2180 ++++++++++++++++++++++
hw/misc/riscv_iopmp_dispatcher.c | 136 ++
hw/misc/trace-events | 4 +
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c | 75 +
include/exec/memory.h | 27 +
include/hw/misc/riscv_iopmp.h | 191 ++
include/hw/misc/riscv_iopmp_dispatcher.h | 61 +
include/hw/misc/riscv_iopmp_txn_info.h | 38 +
include/hw/riscv/virt.h | 4 +
system/memory.c | 104 ++
system/physmem.c | 4 +
system/trace-events | 2 +
target/riscv/cpu.c | 3 +
target/riscv/cpu_cfg.h | 2 +
target/riscv/cpu_helper.c | 18 +-
23 files changed, 2888 insertions(+), 10 deletions(-)
create mode 100644 hw/misc/riscv_iopmp.c
create mode 100644 hw/misc/riscv_iopmp_dispatcher.c
create mode 100644 include/hw/misc/riscv_iopmp.h
create mode 100644 include/hw/misc/riscv_iopmp_dispatcher.h
create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
--
2.34.1
- [PATCH v9 0/8] Support RISC-V IOPMP,
Ethan Chen <=
- [PATCH v9 1/8] hw/core: Add config stream, Ethan Chen, 2025/01/08
- [PATCH v9 2/8] memory: Introduce memory region fetch operation, Ethan Chen, 2025/01/08
- [PATCH v9 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size, Ethan Chen, 2025/01/08
- [PATCH v9 4/8] target/riscv: Add support for IOPMP, Ethan Chen, 2025/01/08
- [PATCH v9 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation, Ethan Chen, 2025/01/08
- [PATCH v9 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device, Ethan Chen, 2025/01/08
- [PATCH v9 8/8] hw/riscv/virt: Add IOPMP support, Ethan Chen, 2025/01/08
- [PATCH v9 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation, Ethan Chen, 2025/01/08