[PATCH v8 0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

[Craig Blackmore]

Thanks Richard for the review on v7. I have updated the patch based on your 
suggestions.

Changes since v7:
- Remove CONFIG_INT128_TYPE guards.
- Strengthen condition for using atomic128.
- Use memcpy for misaligned accesses.
- Hoist atomic operation selection higher up the call stack.

Previous versions:
- v1: 
https://lore.kernel.org/all/20240717153040.11073-1-paolo.savini@embecosm.com/
- v2: 
https://lore.kernel.org/all/20241002135708.99146-1-paolo.savini@embecosm.com/
- v3: 
https://lore.kernel.org/all/20241014220153.196183-1-paolo.savini@embecosm.com/
- v4: 
https://lore.kernel.org/all/20241029194348.59574-1-paolo.savini@embecosm.com/
- v5: 
https://lore.kernel.org/all/20241211143118.661268-1-craig.blackmore@embecosm.com/
- v6: 
https://lore.kernel.org/all/20241218142937.1028602-1-craig.blackmore@embecosm.com/
- v7: 
https://lore.kernel.org/all/20241220122109.2083215-1-craig.blackmore@embecosm.com/

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>

Craig Blackmore (1):
  target/riscv: rvv: Use wider accesses for unit stride load/store

 target/riscv/vector_helper.c | 90 ++++++++++++++++++++++++++++++++----
 1 file changed, 82 insertions(+), 8 deletions(-)

-- 
2.43.0