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Re: [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for A


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v3 3/3] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
Date: Tue, 7 Jan 2025 20:29:27 +0100
User-agent: Mozilla Thunderbird

On 14/11/24 10:48, Jamin Lin wrote:
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).

According to the design of AST2600 EVB, the Write Protected pin is active
high by default. To support it, introduces a new "sdhci_wp_inverted"
property in ASPEED MACHINE State and set it true for AST2600 EVB
and set "wp_inverted" property true of sdhci-generic model.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
---
  hw/arm/aspeed.c         | 7 +++++++
  include/hw/arm/aspeed.h | 1 +
  2 files changed, 8 insertions(+)

Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>




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