Re: [PATCH 1/2] target/riscv: use RISCVException enum in exception helpers

[Alistair Francis]

On Fri, Dec 20, 2024 at 3:49 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Do a cosmetic change in riscv_raise_exception() to change 'exception'
> type from uint32_t to RISCVException, making it a bit clear that the
> arg is directly correlated to the RISCVException enum.
>
> As a side effect, change 'excp' type from int to RISCVException in
> generate_exception() to guarantee that all callers of
> riscv_raise_exception() will use the enum.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h       | 3 ++-
>  target/riscv/op_helper.c | 3 ++-
>  target/riscv/translate.c | 2 +-
>  3 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 284b112821..2b85e558f7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -603,7 +603,8 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong 
> newpriv, bool virt_en);
>
>  void riscv_translate_init(void);
>  G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> -                                      uint32_t exception, uintptr_t pc);
> +                                      RISCVException exception,
> +                                      uintptr_t pc);
>
>  target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index eddedacf4b..29c104bc23 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -27,7 +27,8 @@
>
>  /* Exceptions processing helpers */
>  G_NORETURN void riscv_raise_exception(CPURISCVState *env,
> -                                      uint32_t exception, uintptr_t pc)
> +                                      RISCVException exception,
> +                                      uintptr_t pc)
>  {
>      CPUState *cs = env_cpu(env);
>      cs->exception_index = exception;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index bccaf8e89a..ebae1807a4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -244,7 +244,7 @@ static void gen_update_pc(DisasContext *ctx, target_long 
> diff)
>      ctx->pc_save = ctx->base.pc_next + diff;
>  }
>
> -static void generate_exception(DisasContext *ctx, int excp)
> +static void generate_exception(DisasContext *ctx, RISCVException excp)
>  {
>      gen_update_pc(ctx, 0);
>      gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
> --
> 2.47.1
>
>