[PATCH 08/13] target/mips: Introduce gen_store_gpr_i32()

[Philippe Mathieu-Daudé]

Similarly to the gen_store_gpr_tl() helper which stores a
target-wide TCG register to the CPU generic purpose registers,
add a helper to store 32-bit TCG register.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/mips/tcg/translate.h | 1 +
 target/mips/tcg/translate.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index e15d631ad2a..d9faa82ff70 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -158,6 +158,7 @@ void gen_move_high32_tl(TCGv ret, TCGv_i64 arg);
 void gen_load_gpr_tl(TCGv t, int reg);
 void gen_load_gpr_i32(TCGv_i32 t, int reg);
 void gen_store_gpr_tl(TCGv t, int reg);
+void gen_store_gpr_i32(TCGv_i32 t, int reg);
 #if defined(TARGET_MIPS64)
 void gen_load_gpr_hi(TCGv_i64 t, int reg);
 void gen_store_gpr_hi(TCGv_i64 t, int reg);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d7c83c863d5..6ac0734d1b2 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1216,6 +1216,14 @@ void gen_store_gpr_tl(TCGv t, int reg)
     }
 }
 
+void gen_store_gpr_i32(TCGv_i32 t, int reg)
+{
+    assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
+    if (reg != 0) {
+        tcg_gen_ext_i32_tl(cpu_gpr[reg], t);
+    }
+}
+
 #if defined(TARGET_MIPS64)
 void gen_load_gpr_hi(TCGv_i64 t, int reg)
 {
-- 
2.45.2