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[PULL 36/50] exec/memtxattr: add process identifier to the transaction a
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From: |
Alistair Francis |
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Subject: |
[PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes |
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Date: |
Thu, 31 Oct 2024 13:53:04 +1000 |
From: Tomasz Jeznach <tjeznach@rivosinc.com>
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241016204038.649340-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/exec/memattrs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..e27c18f3dc 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -52,6 +52,11 @@ typedef struct MemTxAttrs {
unsigned int memory:1;
/* Requester ID (for MSI for example) */
unsigned int requester_id:16;
+
+ /*
+ * PID (PCI PASID) support: Limited to 8 bits process identifier.
+ */
+ unsigned int pid:8;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
--
2.47.0
- [PULL 31/50] target/riscv: implement zicfiss instructions, (continued)
- [PULL 31/50] target/riscv: implement zicfiss instructions, Alistair Francis, 2024/10/30
- [PULL 32/50] target/riscv: compressed encodings for sspush and sspopchk, Alistair Francis, 2024/10/30
- [PULL 33/50] disas/riscv: enable disassembly for zicfiss instructions, Alistair Francis, 2024/10/30
- [PULL 34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk, Alistair Francis, 2024/10/30
- [PULL 37/50] hw/riscv: add riscv-iommu-bits.h, Alistair Francis, 2024/10/30
- [PULL 39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device, Alistair Francis, 2024/10/30
- [PULL 40/50] hw/riscv: add riscv-iommu-pci reference device, Alistair Francis, 2024/10/30
- [PULL 41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug, Alistair Francis, 2024/10/30
- [PULL 42/50] test/qtest: add riscv-iommu-pci tests, Alistair Francis, 2024/10/30
- [PULL 35/50] target/riscv: Expose zicfiss extension as a cpu property, Alistair Francis, 2024/10/30
- [PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes,
Alistair Francis <=
- [PULL 38/50] hw/riscv: add RISC-V IOMMU base emulation, Alistair Francis, 2024/10/30
- [PULL 45/50] hw/riscv/riscv-iommu: add DBG support, Alistair Francis, 2024/10/30
- [PULL 43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC), Alistair Francis, 2024/10/30
- [PULL 47/50] docs/specs: add riscv-iommu, Alistair Francis, 2024/10/30
- [PULL 46/50] qtest/riscv-iommu-test: add init queues test, Alistair Francis, 2024/10/30
- [PULL 44/50] hw/riscv/riscv-iommu: add ATS support, Alistair Francis, 2024/10/30
- [PULL 49/50] target/riscv/kvm: clarify how 'riscv-aia' default works, Alistair Francis, 2024/10/30
- [PULL 50/50] target/riscv: Fix vcompress with rvv_ta_all_1s, Alistair Francis, 2024/10/30
- [PULL 48/50] target/riscv/kvm: set 'aia_mode' to default in error path, Alistair Francis, 2024/10/30