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[PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap
From: |
Zhenzhong Duan |
Subject: |
[PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting |
Date: |
Mon, 30 Sep 2024 17:26:30 +0800 |
This gives user flexibility to turn off FS1GP for debug purpose.
It is also useful for future nesting feature. When host IOMMU doesn't
support FS1GP but vIOMMU does, nested page table on host side works
after turn FS1GP off in vIOMMU.
This property has no effect when vIOMMU isn't in scalable modern
mode.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
---
include/hw/i386/intel_iommu.h | 1 +
hw/i386/intel_iommu.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 48134bda11..4d6acb2314 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -307,6 +307,7 @@ struct IntelIOMMUState {
bool dma_drain; /* Whether DMA r/w draining enabled */
bool dma_translation; /* Whether DMA translation supported */
bool pasid; /* Whether to support PASID */
+ bool fs1gp; /* First Stage 1-GByte Page Support */
/*
* Protects IOMMU states in general. Currently it protects the
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 14578655e1..f8f196aeed 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3785,6 +3785,7 @@ static Property vtd_properties[] = {
DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation,
true),
+ DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true),
DEFINE_PROP_END_OF_LIST(),
};
@@ -4513,7 +4514,9 @@ static void vtd_cap_init(IntelIOMMUState *s)
/* TODO: read cap/ecap from host to decide which cap to be exposed. */
if (s->scalable_modern) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
- s->cap |= VTD_CAP_FS1GP;
+ if (s->fs1gp) {
+ s->cap |= VTD_CAP_FS1GP;
+ }
} else if (s->scalable_mode) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
}
--
2.34.1
- [PATCH v4 06/17] intel_iommu: Implement stage-1 translation, (continued)
- [PATCH v4 06/17] intel_iommu: Implement stage-1 translation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 07/17] intel_iommu: Check if the input address is canonical, Zhenzhong Duan, 2024/09/30
- [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 10/17] intel_iommu: Process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/09/30
- [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/09/30
- [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap, Zhenzhong Duan, 2024/09/30
- [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for scalable modern mode, Zhenzhong Duan, 2024/09/30
- [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode, Zhenzhong Duan, 2024/09/30
- [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting,
Zhenzhong Duan <=
- [PATCH v4 17/17] tests/qtest: Add intel-iommu test, Zhenzhong Duan, 2024/09/30