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[PULL v2 09/47] target/riscv: Stop timer with infinite timecmp
From: |
Alistair Francis |
Subject: |
[PULL v2 09/47] target/riscv: Stop timer with infinite timecmp |
Date: |
Wed, 25 Sep 2024 08:17:10 +1000 |
From: Andrew Jones <ajones@ventanamicro.com>
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once again less than timecmp. For this reason
riscv_timer_write_timecmp() special cases UINT64_MAX. However, if a
previously set timecmp has not yet expired, then setting timecmp to
UINT64_MAX to disable / stop it would not work, as the special case
left the previous QEMU timer active, which would then still deliver
an interrupt at that previous timecmp time. Ensure the stopped timer
will not still deliver an interrupt by also deleting the QEMU timer
in the UINT64_MAX special case.
Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp
== UINT64_MAX")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240829084002.1805006-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/time_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 8d245bed3a..bc0d9a0c4c 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -92,6 +92,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer
*timer,
* equals UINT64_MAX.
*/
if (timecmp == UINT64_MAX) {
+ timer_del(timer);
return;
}
--
2.46.1
- [PULL v2 00/47] riscv-to-apply queue, Alistair Francis, 2024/09/24
- [PULL v2 01/47] target/riscv: Add a property to set vl to ceil(AVL/2), Alistair Francis, 2024/09/24
- [PULL v2 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V, Alistair Francis, 2024/09/24
- [PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V, Alistair Francis, 2024/09/24
- [PULL v2 04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V, Alistair Francis, 2024/09/24
- [PULL v2 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule, Alistair Francis, 2024/09/24
- [PULL v2 06/47] target/riscv: fix za64rs enabling, Alistair Francis, 2024/09/24
- [PULL v2 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU, Alistair Francis, 2024/09/24
- [PULL v2 08/47] target/riscv/kvm: Fix the group bit setting of AIA, Alistair Francis, 2024/09/24
- [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp,
Alistair Francis <=
- [PULL v2 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension, Alistair Francis, 2024/09/24
- [PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc, Alistair Francis, 2024/09/24
- [PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support, Alistair Francis, 2024/09/24
- [PULL v2 13/47] target/riscv: Add textra matching condition for the triggers, Alistair Francis, 2024/09/24
- [PULL v2 14/47] exec/memtxattr: add process identifier to the transaction attributes, Alistair Francis, 2024/09/24
- [PULL v2 15/47] hw/riscv: add riscv-iommu-bits.h, Alistair Francis, 2024/09/24
- [PULL v2 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device, Alistair Francis, 2024/09/24
- [PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation, Alistair Francis, 2024/09/24