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[PULL 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V
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From: |
Alistair Francis |
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Subject: |
[PULL 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V |
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Date: |
Thu, 12 Sep 2024 15:29:07 +1000 |
From: Haibo Xu <haibo1.xu@intel.com>
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<0e30216273f2f59916bc651350578d8e8bc3a75f.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/riscv64/virt/SRAT.numamem | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/riscv64/virt/SRAT.numamem
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..a3e01d2eb7 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/SRAT.numamem",
diff --git a/tests/data/acpi/riscv64/virt/SRAT.numamem
b/tests/data/acpi/riscv64/virt/SRAT.numamem
new file mode 100644
index 0000000000..e69de29bb2
--
2.46.0
- [PULL 00/47] riscv-to-apply queue, Alistair Francis, 2024/09/12
- [PULL 01/47] target/riscv: Add a property to set vl to ceil(AVL/2), Alistair Francis, 2024/09/12
- [PULL 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V,
Alistair Francis <=
- [PULL 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V, Alistair Francis, 2024/09/12
- [PULL 04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V, Alistair Francis, 2024/09/12
- [PULL 06/47] target/riscv: fix za64rs enabling, Alistair Francis, 2024/09/12
- [PULL 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule, Alistair Francis, 2024/09/12
- [PULL 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU, Alistair Francis, 2024/09/12
- [PULL 08/47] target/riscv/kvm: Fix the group bit setting of AIA, Alistair Francis, 2024/09/12
- [PULL 09/47] target/riscv: Stop timer with infinite timecmp, Alistair Francis, 2024/09/12
- [PULL 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension, Alistair Francis, 2024/09/12
- [PULL 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc, Alistair Francis, 2024/09/12
- [PULL 12/47] target/riscv: Preliminary textra trigger CSR writting support, Alistair Francis, 2024/09/12