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[PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host
From: |
LIU Zhiwei |
Subject: |
[PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host |
Date: |
Wed, 11 Sep 2024 21:26:30 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index e6d66cd1b9..d27007f2e6 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -143,9 +143,11 @@ typedef enum {
#define TCG_TARGET_HAS_tst 0
/* vector instructions */
-#define TCG_TARGET_HAS_v64 0
-#define TCG_TARGET_HAS_v128 0
-#define TCG_TARGET_HAS_v256 0
+#define have_rvv (cpuinfo & CPUINFO_ZVE64X)
+
+#define TCG_TARGET_HAS_v64 have_rvv
+#define TCG_TARGET_HAS_v128 have_rvv
+#define TCG_TARGET_HAS_v256 have_rvv
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_nand_vec 0
--
2.43.0
- Re: [PATCH v4 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops, (continued)
- [PATCH v4 07/12] tcg/riscv: Implement vector neg ops, LIU Zhiwei, 2024/09/11
- [PATCH v4 05/12] tcg/riscv: Add support for basic vector opcodes, LIU Zhiwei, 2024/09/11
- [PATCH v4 08/12] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/09/11
- [PATCH v4 09/12] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/09/11
- [PATCH v4 10/12] tcg/riscv: Implement vector shi/s/v ops, LIU Zhiwei, 2024/09/11
- [PATCH v4 11/12] tcg/riscv: Implement vector roti/v/x ops, LIU Zhiwei, 2024/09/11
- [PATCH v4 12/12] tcg/riscv: Enable native vector support for TCG host,
LIU Zhiwei <=
- [PATCH v4 01/12] util: Add RISC-V vector extension probe in cpuinfo, LIU Zhiwei, 2024/09/11
- [PATCH v4 02/12] tcg/riscv: Add basic support for vector, LIU Zhiwei, 2024/09/11