Re: [PATCH v3 00/14] Add support for vector

[LIU Zhiwei]

On 2024/9/6 7:46, Alistair Francis wrote:
> On Thu, Sep 5, 2024 at 12:29 AM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
> > From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> Can you please mention RISC-V in the cover letter title. Otherwise
> it's not obvious that this is RISC-V specific
Sorry. I miss it.

Thanks,
Zhiwei

> Alistair
>
> > This patch set introduces support for the RISC-V vector extension
> > in TCG backend for RISC-V targets.
> >
> > v3:
> >    1. Use the .insn form in cpuinfo probing.
> >
> >    2. Use reserved_regs to constrain the register group index instead of using 
> > constrain.
> >
> >    3. Avoid using macros to implement functions whenever possible.
> >
> >    4. Rename vtypei to vtype.
> >
> >    5. Move the __thread prev_vtype variable to TCGContext.
> >
> >    6. Support fractional LMUL setting, but since MF2 has a minimum ELEN of 32,
> >      restrict fractional LMUL to cases where SEW < 64.
> >
> >    7. Handle vector load/store imm12 split in a different function.
> >
> >    8. Remove compare vx and implement INDEX_op_cmpsel_vec for INDEX_op_cmp_vec 
> > in a more concise way.
> >
> >    9. Move the implementation of shi_vec from tcg_expand_vec_op to 
> > tcg_out_vec_op.
> >
> >    10. Address some formatting issues.
> >
> > v2:
> >    https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00679.html
> >
> > v1:
> >    https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00205.html
> >
> > Swung0x48 (1):
> >    tcg/riscv: Add basic support for vector
> >
> > TANG Tiancheng (13):
> >    tcg/op-gvec: Fix iteration step in 32-bit operation
> >    util: Add RISC-V vector extension probe in cpuinfo
> >    tcg/riscv: Add riscv vset{i}vli support
> >    tcg/riscv: Implement vector load/store
> >    tcg/riscv: Implement vector mov/dup{m/i}
> >    tcg/riscv: Add support for basic vector opcodes
> >    tcg/riscv: Implement vector cmp ops
> >    tcg/riscv: Implement vector neg ops
> >    tcg/riscv: Implement vector sat/mul ops
> >    tcg/riscv: Implement vector min/max ops
> >    tcg/riscv: Implement vector shs/v ops
> >    tcg/riscv: Implement vector roti/v/x shi ops
> >    tcg/riscv: Enable native vector support for TCG host
> >
> >   host/include/riscv/host/cpuinfo.h |    3 +
> >   include/tcg/tcg.h                 |    3 +
> >   tcg/riscv/tcg-target-con-set.h    |    7 +
> >   tcg/riscv/tcg-target-con-str.h    |    3 +
> >   tcg/riscv/tcg-target.c.inc        | 1047 ++++++++++++++++++++++++++---
> >   tcg/riscv/tcg-target.h            |   80 ++-
> >   tcg/riscv/tcg-target.opc.h        |   12 +
> >   tcg/tcg-internal.h                |    2 +
> >   tcg/tcg-op-gvec.c                 |    2 +-
> >   tcg/tcg-op-vec.c                  |    2 +-
> >   util/cpuinfo-riscv.c              |   26 +-
> >   11 files changed, 1062 insertions(+), 125 deletions(-)
> >   create mode 100644 tcg/riscv/tcg-target.opc.h
> >
> > --
> > 2.43.0