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[PATCH v2 11/14] tcg/riscv: Implement vector min/max ops
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v2 11/14] tcg/riscv: Implement vector min/max ops |
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Date: |
Fri, 30 Aug 2024 14:16:04 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 01d03a9208..7de2da3571 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -329,6 +329,11 @@ typedef enum {
OPC_VSADDU_VV = 0x80000057 | V_OPIVV,
OPC_VSSUBU_VV = 0x88000057 | V_OPIVV,
+ OPC_VMAX_VV = 0x1c000057 | V_OPIVV,
+ OPC_VMAXU_VV = 0x18000057 | V_OPIVV,
+ OPC_VMIN_VV = 0x14000057 | V_OPIVV,
+ OPC_VMINU_VV = 0x10000057 | V_OPIVV,
+
OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
@@ -2425,6 +2430,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
riscv_set_vec_config_vl_vece(s, type, vece);
tcg_out_opc_vv(s, OPC_VSSUBU_VV, a0, a1, a2, true);
break;
+ case INDEX_op_smax_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
+ tcg_out_opc_vv(s, OPC_VMAX_VV, a0, a1, a2, true);
+ break;
+ case INDEX_op_smin_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
+ tcg_out_opc_vv(s, OPC_VMIN_VV, a0, a1, a2, true);
+ break;
+ case INDEX_op_umax_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
+ tcg_out_opc_vv(s, OPC_VMAXU_VV, a0, a1, a2, true);
+ break;
+ case INDEX_op_umin_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
+ tcg_out_opc_vv(s, OPC_VMINU_VV, a0, a1, a2, true);
+ break;
case INDEX_op_rvv_cmp_vx:
riscv_set_vec_config_vl_vece(s, type, vece);
tcg_out_cmp_vec_vx(s, a2, a0, a1);
@@ -2558,6 +2579,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
return 1;
case INDEX_op_cmp_vec:
return -1;
@@ -2724,6 +2749,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
return C_O1_I2(v, v, v);
case INDEX_op_rvv_merge_vec:
return C_O1_I2(v, v, vK);
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 21251f8b23..35e7086ad7 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -162,7 +162,7 @@ typedef enum {
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
--
2.43.0
- [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation, (continued)
- [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation, LIU Zhiwei, 2024/08/30
- [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo, LIU Zhiwei, 2024/08/30
- [PATCH v2 03/14] tcg/riscv: Add basic support for vector, LIU Zhiwei, 2024/08/30
- [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support, LIU Zhiwei, 2024/08/30
- [PATCH v2 05/14] tcg/riscv: Implement vector load/store, LIU Zhiwei, 2024/08/30
- [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i}, LIU Zhiwei, 2024/08/30
- [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes, LIU Zhiwei, 2024/08/30
- [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 09/14] tcg/riscv: Implement vector neg ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops,
LIU Zhiwei <=
- [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host, LIU Zhiwei, 2024/08/30