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Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv tr
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions |
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Date: |
Tue, 27 Aug 2024 15:47:40 +1000 |
On Tue, Aug 27, 2024 at 2:29 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/27/24 14:03, Alistair Francis wrote:
> > On Tue, Aug 27, 2024 at 1:58 PM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 8/27/24 13:53, Alistair Francis wrote:
> >>> Exposing the *envcfg CSRs to userspace seems tricky as everything is
> >>> currently built with the S/M CSRs removed from user builds.
> >>
> >> It is as simple as moving them out of ifdefs, then initializing them as
> >> needed in reset
> >> for CONFIG_USER_ONLY. That's what we do for Arm.
> >
> > Is that really better though?
> >
> > Then we have these CSRs that are included in the build, so people can
> > write code that checks the CSRs, but they are never actually changed.
> >
> > I guess it simplified the CONFIG_USER_ONLY checks, which is handy and
> > your original point. But it seems like it is clunky that we have these
> > CSRs that are kind of fake
>
> They're not fake. They're a reflection of how the system-mode kernel
> configures the
> system-mode user environment.
>
> The u[bf]cfien variables introduced in this patch set are an indication of
> this. Within
> this patch set they're always false. But the intent is to implement the
> (proposed) prctl
> syscalls that will set them to true (on hold waiting for kernel abi to land
> upstream, but
> were present in an earlier patch set revision.)
>
> The correct implementation of those syscalls, in my opinion, is to set the
> corresponding
> [ms]envcfg bits. Just as linux-user/aarch64/target_prctl.h does for SVE et
> al.
Yeah, that actually does sound better.
That sounds like the way to go then
Alistair
- [PATCH v9 02/17] target/riscv: Introduce elp state and enabling controls for zicfilp, (continued)
- [PATCH v9 02/17] target/riscv: Introduce elp state and enabling controls for zicfilp, Deepak Gupta, 2024/08/26
- [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Deepak Gupta, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Richard Henderson, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Deepak Gupta, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Richard Henderson, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Alistair Francis, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Richard Henderson, 2024/08/26
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Alistair Francis, 2024/08/27
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions, Richard Henderson, 2024/08/27
- Re: [PATCH v9 03/17] target/riscv: save and restore elp state on priv transitions,
Alistair Francis <=
[PATCH v9 05/17] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/26
[PATCH v9 04/17] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/26
[PATCH v9 07/17] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/26
[PATCH v9 09/17] target/riscv: introduce ssp and enabling controls for zicfiss, Deepak Gupta, 2024/08/26
[PATCH v9 12/17] target/riscv: AMO operations always raise store/AMO fault, Deepak Gupta, 2024/08/26
[PATCH v9 06/17] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/26