[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and res
From: |
Ajeet Singh |
Subject: |
[PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions |
Date: |
Sat, 17 Aug 2024 03:09:35 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 5b436b2ac9..bdb527573b 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -130,4 +130,18 @@ static inline void target_cpu_loop(CPURISCVState *env)
}
}
+static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong
newsp)
+{
+ if (newsp) {
+ env->gpr[xSP] = newsp;
+ }
+
+ env->gpr[xA0] = 0; /* a0 */
+ env->gpr[xT0] = 0; /* t0 */
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
- [PATCH v2 00/17] bsd-user: Comprehensive RISCV Support, Ajeet Singh, 2024/08/16
- [PATCH v2 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/16
- [PATCH v2 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/16
- [PATCH v2 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions,
Ajeet Singh <=
- [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/16
- [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/08/16
- [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/16
- [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions, Ajeet Singh, 2024/08/16
- [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/16
- [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/08/16
- [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/16
- [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/16