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[PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loo
From: |
Ajeet Singh |
Subject: |
[PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop |
Date: |
Fri, 2 Aug 2024 18:34:06 +1000 |
From: Mark Corbin <mark.corbin@embecsom.com>
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
---
bsd-user/riscv/target_arch_cpu.h | 39 ++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_cpu.h
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
new file mode 100644
index 0000000000..28f56560e0
--- /dev/null
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -0,0 +1,39 @@
+/*
+ * RISC-V CPU init and loop
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_CPU_H
+#define TARGET_ARCH_CPU_H
+
+#include "target_arch.h"
+
+#define TARGET_DEFAULT_CPU_MODEL "max"
+
+static inline void target_cpu_init(CPURISCVState *env,
+ struct target_pt_regs *regs)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ env->gpr[i] = regs->regs[i];
+ }
+
+ env->pc = regs->sepc;
+}
+
+#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
- [PATCH 00/18] bsd-user: Comprehensive RISCV support, Ajeet Singh, 2024/08/02
- [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop,
Ajeet Singh <=
- [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/02
- [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/02
- [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/02
- [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup, Ajeet Singh, 2024/08/02
- [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/02