On Fri, 24 May 2024 11:05:04 +0100
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
These are very similar to the recently added Generic Initiators
but instead of representing an initiator of memory traffic they
represent an edge point beyond which may lie either targets or
initiators. Here we add these ports such that they may
be targets of hmat_lb records to describe the latency and
bandwidth from host side initiators to the port. A descoverable
mechanism such as UEFI CDAT read from CXL devices and switches
is used to discover the remainder fo the path and the OS can build
up full latency and bandwidth numbers as need for work and data
placement decisions.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To join up the streams. The tests added in this series failed
CI on s390 bios-tables-test.
ad6d572b-f39e-43ff-b11b-74fbe8ae3148@linaro.org/T/#m0f6531d67ba28663bd35b359e32ddfea42db2dea">https://lore.kernel.org/qemu-devel/ad6d572b-f39e-43ff-b11b-74fbe8ae3148@linaro.org/T/#m0f6531d67ba28663bd35b359e32ddfea42db2dea
has my current theory on why and Richard is grabbing the SRAT table
which will hopefully have this as the smoking gun.
Comes back to my normal question to management. Can I have an s390
for tests? Where are those up to date big endian test boxes for
every developer to have on their desks?