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[PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA
From: |
Alistair Francis |
Subject: |
[PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA |
Date: |
Mon, 3 Jun 2024 21:16:41 +1000 |
From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.
However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.
Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.
[1]
https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 473416649f..235e2cdaca 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1777,7 +1777,14 @@ void kvm_riscv_aia_create(MachineState *machine,
uint64_t group_shift,
}
}
- hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+ if (max_hart_per_socket > 1) {
+ max_hart_per_socket--;
+ hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+ } else {
+ hart_bits = 0;
+ }
+
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
&hart_bits, true, NULL);
--
2.45.1
- [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions, (continued)
- [PULL v2 18/27] target/riscv: rvv: Check single width operator for vector fp widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 16/27] riscv: thead: Add th.sxstatus CSR emulation, Alistair Francis, 2024/06/03
- [PULL v2 19/27] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w, Alistair Francis, 2024/06/03
- [PULL v2 20/27] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions, Alistair Francis, 2024/06/03
- [PULL v2 22/27] target/riscv: do not set mtval2 for non guest-page faults, Alistair Francis, 2024/06/03
- [PULL v2 23/27] target/riscv: Remove experimental prefix from "B" extension, Alistair Francis, 2024/06/03
- [PULL v2 21/27] target/riscv: prioritize pmp errors in raise_mmu_exception(), Alistair Francis, 2024/06/03
- [PULL v2 24/27] target/riscv: rvzicbo: Fixup CBO extension register calculation, Alistair Francis, 2024/06/03
- [PULL v2 26/27] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature(), Alistair Francis, 2024/06/03
- [PULL v2 27/27] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs, Alistair Francis, 2024/06/03
- [PULL v2 25/27] target/riscv/kvm.c: Fix the hart bit setting of AIA,
Alistair Francis <=
- Re: [PULL v2 00/27] riscv-to-apply queue, Philippe Mathieu-Daudé, 2024/06/03
- Re: [PULL v2 00/27] riscv-to-apply queue, Richard Henderson, 2024/06/04