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[PULL 10/37] hw/intc/arm_gicv3: Add external IRQ lines for NMI
From: |
Peter Maydell |
Subject: |
[PULL 10/37] hw/intc/arm_gicv3: Add external IRQ lines for NMI |
Date: |
Thu, 25 Apr 2024 11:39:31 +0100 |
From: Jinjie Ruan <ruanjinjie@huawei.com>
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/arm_gic_common.h | 2 ++
include/hw/intc/arm_gicv3_common.h | 2 ++
hw/intc/arm_gicv3_common.c | 6 ++++++
3 files changed, 10 insertions(+)
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index 70803750081..97fea4102d3 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -71,6 +71,8 @@ struct GICState {
qemu_irq parent_fiq[GIC_NCPU];
qemu_irq parent_virq[GIC_NCPU];
qemu_irq parent_vfiq[GIC_NCPU];
+ qemu_irq parent_nmi[GIC_NCPU];
+ qemu_irq parent_vnmi[GIC_NCPU];
qemu_irq maintenance_irq[GIC_NCPU];
/* GICD_CTLR; for a GIC with the security extensions the NS banked version
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index 4e2fb518e72..7324c7d983f 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -155,6 +155,8 @@ struct GICv3CPUState {
qemu_irq parent_fiq;
qemu_irq parent_virq;
qemu_irq parent_vfiq;
+ qemu_irq parent_nmi;
+ qemu_irq parent_vnmi;
/* Redistributor */
uint32_t level; /* Current IRQ level */
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index cb55c726810..c52f060026a 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -299,6 +299,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s,
qemu_irq_handler handler,
for (i = 0; i < s->num_cpu; i++) {
sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
}
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_nmi);
+ }
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi);
+ }
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
"gicv3_dist", 0x10000);
--
2.34.1
- [PULL 00/37] target-arm queue, Peter Maydell, 2024/04/25
- [PULL 02/37] target/arm: Add PSTATE.ALLINT, Peter Maydell, 2024/04/25
- [PULL 03/37] target/arm: Add support for FEAT_NMI, Non-maskable Interrupt, Peter Maydell, 2024/04/25
- [PULL 04/37] target/arm: Implement ALLINT MSR (immediate), Peter Maydell, 2024/04/25
- [PULL 01/37] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI, Peter Maydell, 2024/04/25
- [PULL 10/37] hw/intc/arm_gicv3: Add external IRQ lines for NMI,
Peter Maydell <=
- [PULL 05/37] target/arm: Support MSR access to ALLINT, Peter Maydell, 2024/04/25
- [PULL 07/37] target/arm: Add support for NMI in arm_phys_excp_target_el(), Peter Maydell, 2024/04/25
- [PULL 06/37] target/arm: Add support for Non-maskable Interrupt, Peter Maydell, 2024/04/25
- [PULL 08/37] target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI, Peter Maydell, 2024/04/25
- [PULL 13/37] hw/intc/arm_gicv3: Add has-nmi property to GICv3 device, Peter Maydell, 2024/04/25
- [PULL 14/37] hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3, Peter Maydell, 2024/04/25
- [PULL 15/37] hw/intc/arm_gicv3: Add irq non-maskable property, Peter Maydell, 2024/04/25
- [PULL 19/37] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Peter Maydell, 2024/04/25
- [PULL 21/37] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Peter Maydell, 2024/04/25
- [PULL 26/37] linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code, Peter Maydell, 2024/04/25