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[RFC PATCH v9 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty
From: |
Jinjie Ruan |
Subject: |
[RFC PATCH v9 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty |
Date: |
Thu, 21 Mar 2024 13:08:08 +0000 |
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it is both necessary to check
whether the pending irq is NMI in gicv3_redist_update_noirqset and
gicv3_update_noirqset. And In irqbetter(), only a non-NMI with the same
priority and a smaller interrupt number can be preempted but not NMI.
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v8:
- Add Reviewed-by.
v7:
- Reorder the irqbetter() code for clarity.
- Eliminate the has_superprio local variable for gicv3_get_priority().
- false -> cs->hpplpi.superprio in gicv3_redist_update_noirqset().
- 0x0 -> false in arm_gicv3_common_reset_hold().
- Clear superprio in several places for hppi, hpplpi and hppvlpi.
v6:
- Put the "extract superprio info" logic into gicv3_get_priority().
- Update the comment in irqbetter().
- Reset the cs->hppi.superprio to 0x0.
- Set hppi.superprio to false for LPI.
v4:
- Replace is_nmi with has_superprio to not a mix NMI and superpriority.
- Update the comment in irqbetter().
- Extract gicv3_get_priority() to avoid code repeat.
---
v3:
- Add missing brace
---
hw/intc/arm_gicv3.c | 69 +++++++++++++++++++++++++++++++++-----
hw/intc/arm_gicv3_common.c | 3 ++
hw/intc/arm_gicv3_redist.c | 3 ++
3 files changed, 66 insertions(+), 9 deletions(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 0b8f79a122..9496a28005 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -21,7 +21,8 @@
#include "hw/intc/arm_gicv3.h"
#include "gicv3_internal.h"
-static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
+static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio,
+ bool has_superprio)
{
/* Return true if this IRQ at this priority should take
* precedence over the current recorded highest priority
@@ -30,14 +31,23 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t
prio)
* is the same as this one (a property which the calling code
* relies on).
*/
- if (prio < cs->hppi.prio) {
- return true;
+ if (prio != cs->hppi.prio) {
+ return prio < cs->hppi.prio;
+ }
+
+ /*
+ * The same priority IRQ with superpriority should signal to the CPU
+ * as it have the priority higher than the labelled 0x80 or 0x00.
+ */
+ if (has_superprio != cs->hppi.superprio) {
+ return has_superprio;
}
+
/* If multiple pending interrupts have the same priority then it is an
* IMPDEF choice which of them to signal to the CPU. We choose to
* signal the one with the lowest interrupt number.
*/
- if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
+ if (irq <= cs->hppi.irq) {
return true;
}
return false;
@@ -129,6 +139,40 @@ static uint32_t gicr_int_pending(GICv3CPUState *cs)
return pend;
}
+static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist,
+ uint8_t *prio, int irq)
+{
+ uint32_t superprio = 0x0;
+
+ if (is_redist) {
+ superprio = extract32(cs->gicr_isuperprio, irq, 1);
+ } else {
+ superprio = *gic_bmp_ptr32(cs->gic->superprio, irq);
+ superprio = superprio & (1 << (irq & 0x1f));
+ }
+
+ if (superprio) {
+ /* DS = 0 & Non-secure NMI */
+ if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
+ ((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) ||
+ (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) {
+ *prio = 0x80;
+ } else {
+ *prio = 0x0;
+ }
+
+ return true;
+ }
+
+ if (is_redist) {
+ *prio = cs->gicr_ipriorityr[irq];
+ } else {
+ *prio = cs->gic->gicd_ipriority[irq];
+ }
+
+ return false;
+}
+
/* Update the interrupt status after state in a redistributor
* or CPU interface has changed, but don't tell the CPU i/f.
*/
@@ -141,6 +185,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
uint8_t prio;
int i;
uint32_t pend;
+ bool has_superprio = false;
/* Find out which redistributor interrupts are eligible to be
* signaled to the CPU interface.
@@ -152,10 +197,11 @@ static void gicv3_redist_update_noirqset(GICv3CPUState
*cs)
if (!(pend & (1 << i))) {
continue;
}
- prio = cs->gicr_ipriorityr[i];
- if (irqbetter(cs, i, prio)) {
+ has_superprio = gicv3_get_priority(cs, true, &prio, i);
+ if (irqbetter(cs, i, prio, has_superprio)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = has_superprio;
seenbetter = true;
}
}
@@ -168,9 +214,11 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
(cs->hpplpi.prio != 0xff)) {
- if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
+ if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio,
+ cs->hpplpi.superprio)) {
cs->hppi.irq = cs->hpplpi.irq;
cs->hppi.prio = cs->hpplpi.prio;
+ cs->hppi.superprio = cs->hpplpi.superprio;
cs->hppi.grp = cs->hpplpi.grp;
seenbetter = true;
}
@@ -213,6 +261,7 @@ static void gicv3_update_noirqset(GICv3State *s, int start,
int len)
int i;
uint8_t prio;
uint32_t pend = 0;
+ bool has_superprio = false;
assert(start >= GIC_INTERNAL);
assert(len > 0);
@@ -240,10 +289,11 @@ static void gicv3_update_noirqset(GICv3State *s, int
start, int len)
*/
continue;
}
- prio = s->gicd_ipriority[i];
- if (irqbetter(cs, i, prio)) {
+ has_superprio = gicv3_get_priority(cs, false, &prio, i);
+ if (irqbetter(cs, i, prio, has_superprio)) {
cs->hppi.irq = i;
cs->hppi.prio = prio;
+ cs->hppi.superprio = has_superprio;
cs->seenbetter = true;
}
}
@@ -293,6 +343,7 @@ void gicv3_full_update_noirqset(GICv3State *s)
for (i = 0; i < s->num_cpu; i++) {
s->cpu[i].hppi.prio = 0xff;
+ s->cpu[i].hppi.superprio = false;
}
/* Note that we can guarantee that these functions will not
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 2d2cea6858..822d99d8b4 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -498,8 +498,11 @@ static void arm_gicv3_common_reset_hold(Object *obj)
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
cs->hppi.prio = 0xff;
+ cs->hppi.superprio = false;
cs->hpplpi.prio = 0xff;
+ cs->hpplpi.superprio = false;
cs->hppvlpi.prio = 0xff;
+ cs->hppvlpi.superprio = false;
/* State in the CPU interface must *not* be reset here, because it
* is part of the CPU's reset domain, not the GIC device's.
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index 7a16a058b1..4118c2f297 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -120,6 +120,7 @@ static void update_for_one_lpi(GICv3CPUState *cs, int irq,
((prio == hpp->prio) && (irq <= hpp->irq))) {
hpp->irq = irq;
hpp->prio = prio;
+ hpp->superprio = false;
/* LPIs and vLPIs are always non-secure Grp1 interrupts */
hpp->grp = GICV3_G1NS;
}
@@ -156,6 +157,7 @@ static void update_for_all_lpis(GICv3CPUState *cs, uint64_t
ptbase,
int i, bit;
hpp->prio = 0xff;
+ hpp->superprio = false;
for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {
address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, 1);
@@ -241,6 +243,7 @@ static void gicv3_redist_update_vlpi_only(GICv3CPUState *cs)
if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) {
cs->hppvlpi.prio = 0xff;
+ cs->hppvlpi.superprio = false;
return;
}
--
2.34.1
- Re: [RFC PATCH v9 06/23] target/arm: Add support for Non-maskable Interrupt, (continued)
- [RFC PATCH v9 10/23] hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 12/23] target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64(), Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 05/23] target/arm: Support MSR access to ALLINT, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 09/23] target/arm: Handle PSTATE.ALLINT on taking an exception, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 11/23] hw/intc/arm_gicv3: Add external IRQ lines for NMI, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 13/23] hw/intc/arm_gicv3: Add irq superpriority information, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 16/23] hw/intc: Enable FEAT_GICv3_NMI Feature, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 15/23] hw/intc/arm_gicv3: Implement GICD_INMIR, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 14/23] hw/intc/arm_gicv3_redist: Implement GICR_INMIR0, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 19/23] hw/intc/arm_gicv3: Implement NMI interrupt prioirty,
Jinjie Ruan <=
- [RFC PATCH v9 20/23] hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update(), Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 18/23] hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read(), Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 17/23] hw/intc/arm_gicv3: Add NMI handling CPU interface registers, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 23/23] hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 21/23] hw/intc/arm_gicv3: Report the VINMI interrupt, Jinjie Ruan, 2024/03/21
- [RFC PATCH v9 22/23] target/arm: Add FEAT_NMI to max, Jinjie Ruan, 2024/03/21
- Re: [RFC PATCH v9 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI, Peter Maydell, 2024/03/21
- Re: [RFC PATCH v9 00/23] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI, Peter Maydell, 2024/03/22