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Re: [PATCH v2 03/10] ppc/spapr|pnv: Remove SAO from pa-features
From: |
David Gibson |
Subject: |
Re: [PATCH v2 03/10] ppc/spapr|pnv: Remove SAO from pa-features |
Date: |
Thu, 14 Mar 2024 13:34:38 +1100 |
On Tue, Mar 12, 2024 at 11:14:12PM +1000, Nicholas Piggin wrote:
> SAO is a page table attribute that strengthens the memory ordering of
> accesses. QEMU with MTTCG does not implement this, so clear it in
> ibm,pa-features. This is an obscure feature that has been removed from
> POWER10 ISA v3.1, there isn't much concern with removing it.
>
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Usually altering a user visible feature like this without versioning
would be a no-no. However, I think it's probably ok here: AFAICT the
feature was basically never used, it didn't work in some cases anyway,
and it's now gone away.
> ---
> hw/ppc/pnv.c | 2 +-
> hw/ppc/spapr.c | 14 ++++++++++----
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 0b47b92baa..aa9786e970 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -150,7 +150,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void
> *fdt)
> uint32_t page_sizes_prop[64];
> size_t page_sizes_prop_size;
> const uint8_t pa_features[] = { 24, 0,
> - 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
> + 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0,
> 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
> 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 55263f0815..3108d7c532 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -233,17 +233,23 @@ static void spapr_dt_pa_features(SpaprMachineState
> *spapr,
> PowerPCCPU *cpu,
> void *fdt, int offset)
> {
> + /*
> + * SSO (SAO) ordering is supported on KVM and thread=single hosts,
> + * but not MTTCG, so disable it. To advertise it, a cap would have
> + * to be added, or support implemented for MTTCG.
> + */
> +
> uint8_t pa_features_206[] = { 6, 0,
> - 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> + 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
> uint8_t pa_features_207[] = { 24, 0,
> - 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
> + 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0,
> 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
> 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
> uint8_t pa_features_300[] = { 66, 0,
> /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> - /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ
> */
> - 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
> + /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> + 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> /* 6: DS207 */
> 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> /* 16: Vector */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [PATCH v2 00/10] misc ppc patches, Nicholas Piggin, 2024/03/12
- [PATCH v2 01/10] ppc: Drop support for POWER9 and POWER10 DD1 chips, Nicholas Piggin, 2024/03/12
- [PATCH v2 02/10] target/ppc: POWER10 does not have transactional memory, Nicholas Piggin, 2024/03/12
- [PATCH v2 03/10] ppc/spapr|pnv: Remove SAO from pa-features, Nicholas Piggin, 2024/03/12
- Re: [PATCH v2 03/10] ppc/spapr|pnv: Remove SAO from pa-features,
David Gibson <=
- [PATCH v2 04/10] ppc/spapr: Remove copy-paste from pa-features, Nicholas Piggin, 2024/03/12
- [PATCH v2 05/10] ppc/spapr: Adjust ibm,pa-features for POWER9, Nicholas Piggin, 2024/03/12
- [PATCH v2 06/10] ppc/spapr: Add pa-features for POWER10 machines, Nicholas Piggin, 2024/03/12
- [PATCH v2 07/10] ppc/pnv: Permit ibm, pa-features set per machine variant, Nicholas Piggin, 2024/03/12
- [PATCH v2 08/10] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits, Nicholas Piggin, 2024/03/12
- [PATCH v2 09/10] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/03/12