[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH for-9.0 v13 1/8] target/riscv/vector_helper.c: set vstart = 0 in
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-9.0 v13 1/8] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() |
Date: |
Wed, 13 Mar 2024 16:30:52 -0300 |
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fe56c007d5..ca79571ae2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4781,6 +4781,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
+ env->vstart = 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
--
2.43.2
- [PATCH for-9.0 v13 0/8] riscv: set vstart_eq_zero on vector insns, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 1/8] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX(),
Daniel Henrique Barboza <=
- [PATCH for-9.0 v13 6/8] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 8/8] target/riscv/vector_helper.c: optimize loops in ldst helpers, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 2/8] trans_rvv.c.inc: set vstart = 0 in int scalar move insns, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 3/8] target/riscv/vector_helpers: do early exit when vstart >= vl, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 5/8] target/riscv: remove 'over' brconds from vector trans, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 4/8] target/riscv: always clear vstart in whole vec move insns, Daniel Henrique Barboza, 2024/03/13
- [PATCH for-9.0 v13 7/8] target/riscv: enable 'vstart_eq_zero' in the end of insns, Daniel Henrique Barboza, 2024/03/13