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Re: Enabling internal errors for VH CXL devices: [was: Re: Questions abo
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From: |
Jonathan Cameron |
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Subject: |
Re: Enabling internal errors for VH CXL devices: [was: Re: Questions about CXL RAS injection test in qemu] |
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Date: |
Fri, 8 Mar 2024 12:59:33 +0000 |
On Fri, 8 Mar 2024 10:01:34 +0800
Yuquan Wang <wangyuquan1236@phytium.com.cn> wrote:
> On 2024-03-07 20:10, jonathan.cameron wrote:
>
> > Hack is fine the relevant device with lspci -tv and then use
> > setpci -s 0d:00.0 0x208.l=0
> > to clear all the mask bits for uncorrectable errors.
>
> Thanks! The suggestions from you and Terry did work!
>
> BTW, is my understanding below about CXL RAS correct?
>
> >> 2) The error injected by "pcie_aer_inject_error" is "protocol & link
> >> errors" of cxl.io?
> >> The error injected by "cxl-inject-uncorrectable-errors" or
> >> "cxl-inject-correctable-error" is "protocol & link errors" of cxl.cachemem
> >>
>
> Many thanks
> Yuuqan
>
Yes. Note the two CXL errors are actually communicated via AER uncorrectable /
correctable internal
error combined with data that is available on the EP in the CXL specific
registers.
Jonathan