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Re: [PATCH v5 06/13] hw/mem/cxl_type3: Add host backend and address spac
From: |
Jonathan Cameron |
Subject: |
Re: [PATCH v5 06/13] hw/mem/cxl_type3: Add host backend and address space handling for DC regions |
Date: |
Thu, 7 Mar 2024 12:16:05 +0000 |
> > > @@ -868,16 +974,24 @@ static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev
> > > *ct3d,
> > > AddressSpace **as,
> > > uint64_t *dpa_offset)
> > > {
> > > - MemoryRegion *vmr = NULL, *pmr = NULL;
> > > + MemoryRegion *vmr = NULL, *pmr = NULL, *dc_mr = NULL;
> > > + uint64_t vmr_size = 0, pmr_size = 0, dc_size = 0;
> > >
> > > if (ct3d->hostvmem) {
> > > vmr = host_memory_backend_get_memory(ct3d->hostvmem);
> > > + vmr_size = memory_region_size(vmr);
> > > }
> > > if (ct3d->hostpmem) {
> > > pmr = host_memory_backend_get_memory(ct3d->hostpmem);
> > > + pmr_size = memory_region_size(pmr);
> > > + }
> > > + if (ct3d->dc.host_dc) {
> > > + dc_mr = host_memory_backend_get_memory(ct3d->dc.host_dc);
> > > + /* Do we want dc_size to be dc_mr->size or not?? */
> >
> > Maybe - definitely don't want to leave this comment here
> > unanswered and I think you enforce it above anyway.
> >
> > So if we get here ct3d->dc.total_capacity ==
> > memory_region_size(ct3d->dc.host_dc);
> > As such we could just not stash total_capacity at all?
>
> I cannot identify a case where these two will be different. But
> total_capacity is referenced at quite some places, it may be nice to have
> it so we do not need to call the function to get the value every time?
I kind of like having it via one path so that there is no confusion
for the reader, but up to you on this one. The function called is trivial
(other than some magic to handle very large memory regions) so
this is just a readability question, not a perf one.
Whatever, don't leave the question behind. Find to have something
that says they are always the same size if you don't get rid
of the total_capacity representation.
Jonathan
- [PATCH v5 04/13] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices, (continued)
- [PATCH v5 04/13] hw/mem/cxl_type3: Add support to create DC regions to type3 memory devices, nifan . cxl, 2024/03/04
- [PATCH v5 05/13] hw/mem/cxl-type3: Refactor ct3_build_cdat_entries_for_mr to take mr size insead of mr as argument, nifan . cxl, 2024/03/04
- [PATCH v5 07/13] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support, nifan . cxl, 2024/03/04
- [PATCH v5 06/13] hw/mem/cxl_type3: Add host backend and address space handling for DC regions, nifan . cxl, 2024/03/04
- Re: [PATCH v5 06/13] hw/mem/cxl_type3: Add host backend and address space handling for DC regions, fan, 2024/03/14
[PATCH v5 08/13] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response, nifan . cxl, 2024/03/04
[PATCH v5 09/13] hw/cxl/events: Add qmp interfaces to add/release dynamic capacity extents, nifan . cxl, 2024/03/04