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[PATCH 4/5] target/riscv: Expose Zve64x extension to users
From: |
Jason Chien |
Subject: |
[PATCH 4/5] target/riscv: Expose Zve64x extension to users |
Date: |
Thu, 7 Mar 2024 01:08:37 +0800 |
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8b5d1eb6a8..58b2a94694 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1473,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
+ MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
--
2.43.2
- [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions, Jason Chien, 2024/03/06
- [PATCH 2/5] target/riscv: Expose Zve32x extension to users, Jason Chien, 2024/03/06
- [PATCH 4/5] target/riscv: Expose Zve64x extension to users,
Jason Chien <=
- [PATCH 3/5] target/riscv: Add support for Zve64x extension, Jason Chien, 2024/03/06
- [PATCH 5/5] target/riscv: Relax vector register check in RISCV gdbstub, Jason Chien, 2024/03/06
- Re: [PATCH 0/5] target/riscv: Support Zve32x and Zve64x extensions, Jason Chien, 2024/03/19