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[PULL 14/20] exec/memattrs: Remove target_tlb_bit*
From: |
Peter Maydell |
Subject: |
[PULL 14/20] exec/memattrs: Remove target_tlb_bit* |
Date: |
Tue, 5 Mar 2024 13:52:31 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
These fields are no longer used since 937f224559.
Target specific extensions to the page tables should be done
with TARGET_PAGE_ENTRY_EXTRA.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240301204110.656742-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/exec/memattrs.h | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d04170aa27a..afa885f9830 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -54,16 +54,6 @@ typedef struct MemTxAttrs {
unsigned int requester_id:16;
/* Invert endianness for this page */
unsigned int byte_swap:1;
- /*
- * The following are target-specific page-table bits. These are not
- * related to actual memory transactions at all. However, this structure
- * is part of the tlb_fill interface, cached in the cputlb structure,
- * and has unused bits. These fields will be read by target-specific
- * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
- */
- unsigned int target_tlb_bit0 : 1;
- unsigned int target_tlb_bit1 : 1;
- unsigned int target_tlb_bit2 : 1;
} MemTxAttrs;
/* Bus masters which don't specify any attributes will get this,
--
2.34.1
- [PULL 12/20] tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC, (continued)
- [PULL 12/20] tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC, Peter Maydell, 2024/03/05
- [PULL 06/20] hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object, Peter Maydell, 2024/03/05
- [PULL 17/20] target/arm: Do memory type alignment check when translation disabled, Peter Maydell, 2024/03/05
- [PULL 19/20] atomic.h: Reword confusing comment for qatomic_cmpxchg, Peter Maydell, 2024/03/05
- [PULL 15/20] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull, Peter Maydell, 2024/03/05
- [PULL 08/20] hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers, Peter Maydell, 2024/03/05
- [PULL 16/20] accel/tcg: Add TLB_CHECK_ALIGNED, Peter Maydell, 2024/03/05
- [PULL 07/20] hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object, Peter Maydell, 2024/03/05
- [PULL 09/20] hw/misc/stm32l4x5_rcc: Handle Register Updates, Peter Maydell, 2024/03/05
- [PULL 02/20] hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2, Peter Maydell, 2024/03/05
- [PULL 14/20] exec/memattrs: Remove target_tlb_bit*,
Peter Maydell <=
- [PULL 20/20] qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports, Peter Maydell, 2024/03/05
- [PULL 01/20] hw/i2c: Implement Broadcom Serial Controller (BSC), Peter Maydell, 2024/03/05
- [PULL 11/20] hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk, Peter Maydell, 2024/03/05
- [PULL 05/20] hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton, Peter Maydell, 2024/03/05
- [PULL 04/20] hw/char/pl011: Add support for loopback, Peter Maydell, 2024/03/05
- [PULL 18/20] target/arm: Do memory type alignment check when translation enabled, Peter Maydell, 2024/03/05
- [PULL 13/20] target/arm: Support 32-byte alignment in pow2_align, Peter Maydell, 2024/03/05
- Re: [PULL 00/20] target-arm queue, Peter Maydell, 2024/03/05
- [PULL 00/20] target-arm queue, Peter Maydell, 2024/03/11