RE: [PATCH v1 7/8] aspeed/soc: Add AST2700 support

[Jamin Lin]

> -----Original Message-----
> From: Philippe Mathieu-Daudé <philmd@linaro.org>
> Sent: Thursday, February 29, 2024 5:38 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; Alistair
> Francis <alistair@alistair23.me>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v1 7/8] aspeed/soc: Add AST2700 support
> 
> Hi Jamin,
> 
> On 29/2/24 08:23, Jamin Lin via wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We introduce a new ast2700 class with
> > instance_init and realize handlers.
> >
> > AST2700 is a 64 bits quad core cpus and support 8 watchdog.
> > Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8.
> > In addition, update AspeedSocState to support scuio, sli, sliio and intc.
> >
> > Update silicon_rev data type to 64bits from AspeedSoCClass and add
> > TYPE_ASPEED27X0_SOC machine type.
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/arm/aspeed_ast27x0.c     | 462
> ++++++++++++++++++++++++++++++++++++
> >   hw/arm/meson.build          |   1 +
> >   include/hw/arm/aspeed_soc.h |  26 +-
> >   3 files changed, 486 insertions(+), 3 deletions(-)
> >   create mode 100644 hw/arm/aspeed_ast27x0.c
> 
> 
> > +#define AST2700_MAX_IRQ 288
> > +
> > +/* Shared Peripheral Interrupt values below are offset by -32 from
> > +datasheet */ static const int aspeed_soc_ast2700_irqmap[] = {
> > +    [ASPEED_DEV_UART0]     = 132,
> > +    [ASPEED_DEV_UART1]     = 132,
> > +    [ASPEED_DEV_UART2]     = 132,
> > +    [ASPEED_DEV_UART3]     = 132,
> > +    [ASPEED_DEV_UART4]     = 8,
> > +    [ASPEED_DEV_UART5]     = 132,
> > +    [ASPEED_DEV_UART6]     = 132,
> > +    [ASPEED_DEV_UART7]     = 132,
> > +    [ASPEED_DEV_UART8]     = 132,
> > +    [ASPEED_DEV_UART9]     = 132,
> > +    [ASPEED_DEV_UART10]    = 132,
> > +    [ASPEED_DEV_UART11]    = 132,
> > +    [ASPEED_DEV_UART12]    = 132,
> 
> When multiple devices output IRQ lines are connected to the same input one,
> a IRQ OR gate has to be used.
> 
> See previous explanations here:
> https://lore.kernel.org/qemu-devel/5a7594d9-3fbd-4d90-a5f9-81b7b845fba7@
> linaro.org/
> 
Thanks for your review and suggestion.
I am studying this design and they will be modified 
in V3 patch series.
Thanks-Jamin

> (Pre-existing issue in aspeed_soc_ast2600_irqmap[])
> 
> > +    [ASPEED_DEV_FMC]       = 131,
> > +    [ASPEED_DEV_SDMC]      = 0,
> > +    [ASPEED_DEV_SCU]       = 12,
> > +    [ASPEED_DEV_ADC]       = 130,
> > +    [ASPEED_DEV_XDMA]      = 5,
> > +    [ASPEED_DEV_EMMC]      = 15,
> > +    [ASPEED_DEV_GPIO]      = 11,
> > +    [ASPEED_DEV_GPIO_1_8V] = 130,
> > +    [ASPEED_DEV_RTC]       = 13,
> > +    [ASPEED_DEV_TIMER1]    = 16,
> > +    [ASPEED_DEV_TIMER2]    = 17,
> > +    [ASPEED_DEV_TIMER3]    = 18,
> > +    [ASPEED_DEV_TIMER4]    = 19,
> > +    [ASPEED_DEV_TIMER5]    = 20,
> > +    [ASPEED_DEV_TIMER6]    = 21,
> > +    [ASPEED_DEV_TIMER7]    = 22,
> > +    [ASPEED_DEV_TIMER8]    = 23,
> > +    [ASPEED_DEV_WDT]       = 131,
> > +    [ASPEED_DEV_PWM]       = 131,
> > +    [ASPEED_DEV_LPC]       = 128,
> > +    [ASPEED_DEV_IBT]       = 128,
> > +    [ASPEED_DEV_I2C]       = 130,
> > +    [ASPEED_DEV_PECI]      = 133,
> > +    [ASPEED_DEV_ETH1]      = 132,
> > +    [ASPEED_DEV_ETH2]      = 132,
> > +    [ASPEED_DEV_ETH3]      = 132,
> > +    [ASPEED_DEV_HACE]      = 4,
> > +    [ASPEED_DEV_KCS]       = 128,
> > +    [ASPEED_DEV_DP]        = 28,
> > +    [ASPEED_DEV_I3C]       = 131,
> > +};