Re: [PATCH v1 6/8] aspeed/intc: Add AST2700 support

[Philippe Mathieu-Daudé]

Hi Jamin,

On 29/2/24 08:23, Jamin Lin via wrote:
> AST2700 interrupt controller(INTC) provides hardware interrupt interfaces
> to interrupt of processors PSP, SSP and TSP. In INTC, each interrupt of
> INT 128 to INT136 combines 32 interrupts.
>
> Introduce a new aspeed_intc class with instance_init and realize handlers.
>
> QEMU supports ARM Generic Interrupt Controller, version 3(GICv3)
> but not support Shared Peripheral Interrupt (SPI), yet.
> This patch added work around to set GICINT132[18] which was BMC UART interrupt
> if it received GICINT132, so users are able to type any key from keyboard to
> trigger GICINT132 interrupt until AST2700 boot into login prompt.
> It is a temporary solution.
>
> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/intc/aspeed_intc.c        | 135 +++++++++++++++++++++++++++++++++++
>   hw/intc/meson.build          |   1 +
>   include/hw/intc/aspeed_vic.h |  29 ++++++++
>   3 files changed, 165 insertions(+)
>   create mode 100644 hw/intc/aspeed_intc.c

> +#define TO_REG(N) (N >> 2)

> +static const MemoryRegionOps aspeed_intc_ops = {
> +    .read = aspeed_intc_read,
> +    .write = aspeed_intc_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
Please be also explicit with the implementation:

      .impl.min_access_size = 4,
      .impl.max_access_size = 4,

> +    .valid.min_access_size = 4,
> +    .valid.max_access_size = 4,
> +    .valid.unaligned = false,
> +};