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[PATCH 3/3] target/hppa: mask CR_SAR register writes to 5/6 bit in gdbst
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From: |
Sven Schnelle |
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Subject: |
[PATCH 3/3] target/hppa: mask CR_SAR register writes to 5/6 bit in gdbstub |
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Date: |
Wed, 28 Feb 2024 21:14:33 +0100 |
Signed-off-by: Sven Schnelle <svens@stackframe.org>
---
target/hppa/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c
index a5b2c80c07..049b2d6381 100644
--- a/target/hppa/gdbstub.c
+++ b/target/hppa/gdbstub.c
@@ -184,7 +184,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
env->gr[n] = val;
break;
case 32:
- env->cr[CR_SAR] = val;
+ env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31);
break;
case 33:
env->iaoq_f = val;
--
2.43.2