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[PATCH 1/5] target/i386/cpu: Expose SMI# IRQ line via QDev
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 1/5] target/i386/cpu: Expose SMI# IRQ line via QDev |
Date: |
Mon, 26 Feb 2024 17:49:08 +0100 |
In order to remove calls to cpu_interrupt() from hw/ code,
expose the SMI# interrupt via QDev as named GPIO.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/cpu-internal.h | 1 +
target/i386/cpu-sysemu.c | 11 +++++++++++
target/i386/cpu.c | 2 ++
3 files changed, 14 insertions(+)
diff --git a/target/i386/cpu-internal.h b/target/i386/cpu-internal.h
index 9baac5c0b4..9d76bb77cf 100644
--- a/target/i386/cpu-internal.h
+++ b/target/i386/cpu-internal.h
@@ -62,6 +62,7 @@ GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs);
void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
const char *name, void *opaque, Error **errp);
+void x86_cpu_smi_irq(void *opaque, int irq, int level);
void x86_cpu_apic_create(X86CPU *cpu, Error **errp);
void x86_cpu_apic_realize(X86CPU *cpu, Error **errp);
void x86_cpu_machine_reset_cb(void *opaque);
diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c
index 7422096737..7684a7f01e 100644
--- a/target/i386/cpu-sysemu.c
+++ b/target/i386/cpu-sysemu.c
@@ -370,3 +370,14 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
qapi_free_GuestPanicInformation(panic_info);
}
+void x86_cpu_smi_irq(void *opaque, int irq, int level)
+{
+ DeviceState *dev = opaque;
+ CPUState *cs = CPU(dev);
+
+ if (level) {
+ cpu_interrupt(cs, CPU_INTERRUPT_SMI);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_SMI);
+ }
+}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f90823676..6b4462d533 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7463,6 +7463,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
}
#ifndef CONFIG_USER_ONLY
+ qdev_init_gpio_in_named(dev, x86_cpu_smi_irq, "SMI", 1);
+
x86_cpu_apic_realize(cpu, &local_err);
if (local_err != NULL) {
goto out;
--
2.41.0
- [RFC PATCH 0/5] hw/i386/q35: Decouple virtual SMI# lines and wire them to ICH9 chipset, Philippe Mathieu-Daudé, 2024/02/26
- [PATCH 1/5] target/i386/cpu: Expose SMI# IRQ line via QDev,
Philippe Mathieu-Daudé <=
- [RFC PATCH 3/5] hw/ahci/ich9_tco: Set CPU SMI# interrupt using QDev GPIO API, Philippe Mathieu-Daudé, 2024/02/26
- [PATCH 2/5] hw/i386/piix: Set CPU SMI# interrupt using QDev GPIO API, Philippe Mathieu-Daudé, 2024/02/26
- [RFC PATCH 4/5] hw/i386/q35: Wire virtual SMI# lines to ICH9 chipset, Philippe Mathieu-Daudé, 2024/02/26
- [RFC PATCH 5/5] hw/isa: Build ich9_lpc.c once, Philippe Mathieu-Daudé, 2024/02/26
- Re: [RFC PATCH 0/5] hw/i386/q35: Decouple virtual SMI# lines and wire them to ICH9 chipset, Laszlo Ersek, 2024/02/27