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[PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written softwar
From: |
Nicholas Piggin |
Subject: |
[PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written software TLB entry |
Date: |
Sat, 24 Feb 2024 01:42:03 +1000 |
BookE software TLB is implemented by flushing old translations from the
relevant TCG TLB whenever software TLB entries change. This means a new
software TLB entry should not have any corresponding cached TCG TLB
translations, so there is nothing to flush. The exception is multiple
software TLBs that cover the same address and address space, but that is
a programming error and results in undefined behaviour, and flushing
does not give an obviously better outcome in that case either.
Remove the unnecessary flush of a newly written software TLB entry.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu_helper.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 949ae87f4f..68632bf54e 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -808,13 +808,6 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong
entry,
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
- /* Invalidate new TLB (if valid) */
- if (tlb->prot & PAGE_VALID) {
- qemu_log_mask(CPU_LOG_MMU, "%s: invalidate TLB %d start "
- TARGET_FMT_lx " end " TARGET_FMT_lx "\n", __func__,
- (int)entry, tlb->EPN, tlb->EPN + tlb->size);
- ppcemb_tlb_flush(cs, tlb);
- }
}
void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry,
--
2.42.0
- [PULL 21/47] misc/pca9552: Fix inverted input status, (continued)
- [PULL 21/47] misc/pca9552: Fix inverted input status, Nicholas Piggin, 2024/02/23
- [PULL 20/47] ppc/pnv: Change powernv default to powernv10, Nicholas Piggin, 2024/02/23
- [PULL 24/47] ppc/pnv: Add pca9552 to powernv10-rainier for PCIe hotplug power control, Nicholas Piggin, 2024/02/23
- [PULL 46/47] target/ppc: 440 optimise tlbwe TLB flushing, Nicholas Piggin, 2024/02/23
- [PULL 29/47] ppc/pnv: Test pnv i2c master and connected devices, Nicholas Piggin, 2024/02/23
- [PULL 37/47] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/23
- [PULL 35/47] target/ppc: Improve timebase register defines naming, Nicholas Piggin, 2024/02/23
- [PULL 32/47] hw/ppc: N1 chiplet wiring, Nicholas Piggin, 2024/02/23
- [PULL 34/47] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/02/23
- [PULL 41/47] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/02/23
- [PULL 44/47] target/ppc: 4xx don't flush TLB for a newly written software TLB entry,
Nicholas Piggin <=
- [PULL 45/47] target/ppc: 4xx optimise tlbwe_lo TLB flushing, Nicholas Piggin, 2024/02/23
- [PULL 07/47] tests/avocado: Add pseries KVM boot_linux test, Nicholas Piggin, 2024/02/23
- [PULL 13/47] hw/ppc/spapr_hcall: Allow elision of softmmu_resize_hpt_prep, Nicholas Piggin, 2024/02/23
- [PULL 16/47] ppc/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs., Nicholas Piggin, 2024/02/23
- [PULL 30/47] hw/ppc: Add pnv nest pervasive common chiplet model, Nicholas Piggin, 2024/02/23
- [PULL 33/47] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/02/23
- [PULL 36/47] target/ppc: Fix move-to timebase SPR access permissions, Nicholas Piggin, 2024/02/23
- [PULL 38/47] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/02/23
- [PULL 40/47] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/02/23
- [PULL 43/47] target/ppc: Factor out 4xx ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/23