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[PULL 48/49] target/ppc: 440 optimise tlbwe TLB flushing
From: |
Nicholas Piggin |
Subject: |
[PULL 48/49] target/ppc: 440 optimise tlbwe TLB flushing |
Date: |
Mon, 19 Feb 2024 18:29:37 +1000 |
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Acked-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/mmu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 923779d052..ba965f1779 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -864,7 +864,7 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word,
target_ulong entry,
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
- tlb_flush(env_cpu(env));
+ ppcemb_tlb_flush(env_cpu(env), tlb);
}
switch (word) {
--
2.42.0
- [PULL 43/49] target/ppc: Add SMT support to time facilities, (continued)
- [PULL 43/49] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/02/19
- [PULL 39/49] ppc/pnv: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/02/19
- [PULL 40/49] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/02/19
- [PULL 44/49] target/ppc: Fix 440 tlbwe TLB invalidation gaps, Nicholas Piggin, 2024/02/19
- [PULL 41/49] ppc/pnv: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/02/19
- [PULL 42/49] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/02/19
- [PULL 45/49] target/ppc: Factor out 4xx ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/19
- [PULL 46/49] target/ppc: 4xx don't flush TLB for a newly written software TLB entry, Nicholas Piggin, 2024/02/19
- [PULL 47/49] target/ppc: 4xx optimise tlbwe_lo TLB flushing, Nicholas Piggin, 2024/02/19
- [PULL 49/49] target/ppc: optimise ppcemb_tlb_t flushing, Nicholas Piggin, 2024/02/19
- [PULL 48/49] target/ppc: 440 optimise tlbwe TLB flushing,
Nicholas Piggin <=
- Re: [PULL 00/49] ppc-for-9.0 queue, Peter Maydell, 2024/02/19