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[PULL 35/57] tcg/loongarch64: Set vector registers call clobbered
From: |
Richard Henderson |
Subject: |
[PULL 35/57] tcg/loongarch64: Set vector registers call clobbered |
Date: |
Fri, 2 Feb 2024 15:50:14 +1000 |
Because there are more call clobbered registers than
call saved registers, we begin with all registers as
call clobbered and then reset those that are saved.
This was missed when we introduced the LSX support.
Cc: qemu-stable@nongnu.org
Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index bab0a173a3..dcf0205458 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -2327,7 +2327,7 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
- tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
+ tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
--
2.34.1
- [PULL 25/57] target/rx: Populate CPUClass.mmu_index, (continued)
- [PULL 25/57] target/rx: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 28/57] target/sh4: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 30/57] target/tricore: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 27/57] target/s390x: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 29/57] target/sparc: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 31/57] target/xtensa: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 26/57] target/s390x: Split out s390x_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 32/57] include/exec: Implement cpu_mmu_index generically, Richard Henderson, 2024/02/02
- [PULL 33/57] include/exec: Change cpu_mmu_index argument to CPUState, Richard Henderson, 2024/02/02
- [PULL 34/57] tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test, Richard Henderson, 2024/02/02
- [PULL 35/57] tcg/loongarch64: Set vector registers call clobbered,
Richard Henderson <=
- [PULL 36/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY, Richard Henderson, 2024/02/02
- [PULL 38/57] target/sparc: Remove gen_dest_fpr_F, Richard Henderson, 2024/02/02
- [PULL 37/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL, Richard Henderson, 2024/02/02
- [PULL 39/57] target/sparc: Introduce gen_{load,store}_fpr_Q, Richard Henderson, 2024/02/02
- [PULL 40/57] target/sparc: Inline FNEG, FABS, Richard Henderson, 2024/02/02
- [PULL 42/57] target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq, Richard Henderson, 2024/02/02
- [PULL 43/57] target/sparc: Use i128 for FqTOs, FqTOi, Richard Henderson, 2024/02/02
- [PULL 44/57] target/sparc: Use i128 for FqTOd, FqTOx, Richard Henderson, 2024/02/02
- [PULL 41/57] target/sparc: Use i128 for FSQRTq, Richard Henderson, 2024/02/02
- [PULL 45/57] target/sparc: Use i128 for FCMPq, FCMPEq, Richard Henderson, 2024/02/02