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[PULL 04/57] target/arm: Split out arm_env_mmu_index
From: |
Richard Henderson |
Subject: |
[PULL 04/57] target/arm: Split out arm_env_mmu_index |
Date: |
Fri, 2 Feb 2024 15:49:43 +1000 |
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 5 +++++
target/arm/helper.c | 2 +-
target/arm/tcg/helper-a64.c | 4 ++--
target/arm/tcg/mte_helper.c | 18 +++++++++---------
target/arm/tcg/sve_helper.c | 8 ++++----
target/arm/tcg/tlb_helper.c | 2 +-
6 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 71d6c70bf3..fc337fe40e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -40,6 +40,11 @@
#define BANK_HYP 6
#define BANK_MON 7
+static inline int arm_env_mmu_index(CPUARMState *env)
+{
+ return EX_TBFLAG_ANY(env->hflags, MMUIDX);
+}
+
static inline bool excp_is_internal(int excp)
{
/* Return true if this exception number represents a QEMU-internal
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 945d8571a6..b0488caf40 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7841,7 +7841,7 @@ static void dccvap_writefn(CPUARMState *env, const
ARMCPRegInfo *opaque,
uint64_t vaddr_in = (uint64_t) value;
uint64_t vaddr = vaddr_in & ~(dline_size - 1);
void *haddr;
- int mem_idx = cpu_mmu_index(env, false);
+ int mem_idx = arm_env_mmu_index(env);
/* This won't be crossing page boundaries */
haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 198b975f20..ebaa7f00df 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -856,7 +856,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
tbii = EX_TBFLAG_A64(env->hflags, TBII);
if ((tbii >> extract64(new_pc, 55, 1)) & 1) {
/* TBI is enabled. */
- int core_mmu_idx = cpu_mmu_index(env, false);
+ int core_mmu_idx = arm_env_mmu_index(env);
if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) {
new_pc = sextract64(new_pc, 0, 56);
} else {
@@ -925,7 +925,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
*/
int blocklen = 4 << env_archcpu(env)->dcz_blocksize;
uint64_t vaddr = vaddr_in & ~(blocklen - 1);
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
void *mem;
/*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index ffb8ea1c34..d971b81370 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -291,7 +291,7 @@ static int load_tag1(uint64_t ptr, uint8_t *mem)
uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uint8_t *mem;
int rtag = 0;
@@ -311,7 +311,7 @@ static void check_tag_aligned(CPUARMState *env, uint64_t
ptr, uintptr_t ra)
{
if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) {
arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE,
- cpu_mmu_index(env, false), ra);
+ arm_env_mmu_index(env), ra);
g_assert_not_reached();
}
}
@@ -344,7 +344,7 @@ typedef void stg_store1(uint64_t, uint8_t *, int);
static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,
uintptr_t ra, stg_store1 store1)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uint8_t *mem;
check_tag_aligned(env, ptr, ra);
@@ -371,7 +371,7 @@ void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr,
uint64_t xt)
void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uintptr_t ra = GETPC();
check_tag_aligned(env, ptr, ra);
@@ -381,7 +381,7 @@ void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,
uintptr_t ra, stg_store1 store1)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
int tag = allocation_tag_from_addr(xt);
uint8_t *mem1, *mem2;
@@ -429,7 +429,7 @@ void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr,
uint64_t xt)
void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uintptr_t ra = GETPC();
int in_page = -(ptr | TARGET_PAGE_MASK);
@@ -445,7 +445,7 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uintptr_t ra = GETPC();
int gm_bs = env_archcpu(env)->gm_blocksize;
int gm_bs_bytes = 4 << gm_bs;
@@ -505,7 +505,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
uintptr_t ra = GETPC();
int gm_bs = env_archcpu(env)->gm_blocksize;
int gm_bs_bytes = 4 << gm_bs;
@@ -555,7 +555,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t
val)
void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
{
uintptr_t ra = GETPC();
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
int log2_dcz_bytes, log2_tag_bytes;
intptr_t dcz_bytes, tag_bytes;
uint8_t *mem;
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index f006d152cc..bce4295d28 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -5481,7 +5481,7 @@ bool sve_cont_ldst_pages(SVEContLdSt *info, SVEContFault
fault,
CPUARMState *env, target_ulong addr,
MMUAccessType access_type, uintptr_t retaddr)
{
- int mmu_idx = cpu_mmu_index(env, false);
+ int mmu_idx = arm_env_mmu_index(env);
int mem_off = info->mem_off_first[0];
bool nofault = fault == FAULT_NO;
bool have_work = true;
@@ -6529,7 +6529,7 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *vg,
void *vm,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const int mmu_idx = cpu_mmu_index(env, false);
+ const int mmu_idx = arm_env_mmu_index(env);
const intptr_t reg_max = simd_oprsz(desc);
const int scale = simd_data(desc);
ARMVectorReg scratch;
@@ -6715,7 +6715,7 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64_t
*vg, void *vm,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const int mmu_idx = cpu_mmu_index(env, false);
+ const int mmu_idx = arm_env_mmu_index(env);
const intptr_t reg_max = simd_oprsz(desc);
const int scale = simd_data(desc);
const int esize = 1 << esz;
@@ -6920,7 +6920,7 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *vg,
void *vm,
sve_ldst1_host_fn *host_fn,
sve_ldst1_tlb_fn *tlb_fn)
{
- const int mmu_idx = cpu_mmu_index(env, false);
+ const int mmu_idx = arm_env_mmu_index(env);
const intptr_t reg_max = simd_oprsz(desc);
const int scale = simd_data(desc);
void *host[ARM_MAX_VQ * 4];
diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c
index 5477c7fb7d..885bf4ec14 100644
--- a/target/arm/tcg/tlb_helper.c
+++ b/target/arm/tcg/tlb_helper.c
@@ -281,7 +281,7 @@ void helper_exception_pc_alignment(CPUARMState *env,
target_ulong pc)
{
ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
int target_el = exception_target_el(env);
- int mmu_idx = cpu_mmu_index(env, true);
+ int mmu_idx = arm_env_mmu_index(env);
uint32_t fsc;
env->exception.vaddress = pc;
--
2.34.1
- [PULL 00/57] tcg patch queue, Richard Henderson, 2024/02/02
- [PULL 01/57] include/hw/core: Add mmu_index to CPUClass, Richard Henderson, 2024/02/02
- [PATCH] linux-user/aarch64: Add padding before __kernel_rt_sigreturn, Richard Henderson, 2024/02/02
- [PULL 02/57] target/alpha: Split out alpha_env_mmu_index, Richard Henderson, 2024/02/02
- [PULL 03/57] target/alpha: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 04/57] target/arm: Split out arm_env_mmu_index,
Richard Henderson <=
- [PULL 05/57] target/arm: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 06/57] target/avr: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 07/57] target/cris: Cache mem_index in DisasContext, Richard Henderson, 2024/02/02
- [PULL 08/57] target/cris: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 09/57] target/hppa: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 10/57] target/i386: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 11/57] target/loongarch: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 12/57] target/loongarch: Rename MMU_IDX_*, Richard Henderson, 2024/02/02
- [PULL 13/57] target/m68k: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02
- [PULL 14/57] target/microblaze: Populate CPUClass.mmu_index, Richard Henderson, 2024/02/02