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[PATCH v8 18/21] hw/i386/pc: Support smp.modules for x86 PC machine
From: |
Zhao Liu |
Subject: |
[PATCH v8 18/21] hw/i386/pc: Support smp.modules for x86 PC machine |
Date: |
Wed, 31 Jan 2024 18:13:47 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
As module-level topology support is added to X86CPU, now we can enable
the support for the modules parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,modules=*,cores=*,threads=*.
Additionally, add the 5-level topology example in description of "-smp".
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Co-developed-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v7:
* Supported modules instead of clusters for PC.
* Dropped Michael/Babu/Yanan's ACKed/Tested/Reviewed tags since the
code change.
* Re-added Yongwei's Tested tag For his re-testing.
---
hw/i386/pc.c | 1 +
qemu-options.hx | 10 +++++-----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 803244e5ccba..22923f26c0e6 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1849,6 +1849,7 @@ static void pc_machine_class_init(ObjectClass *oc, void
*data)
mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
+ mc->smp_props.modules_supported = true;
mc->default_ram_id = "pc.ram";
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64;
diff --git a/qemu-options.hx b/qemu-options.hx
index ced828486376..e164ecb60367 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -345,14 +345,14 @@ SRST
-smp 8,sockets=2,cores=2,threads=2,maxcpus=8
The following sub-option defines a CPU topology hierarchy (2 sockets
- totally on the machine, 2 dies per socket, 2 cores per die, 2 threads
- per core) for PC machines which support sockets/dies/cores/threads.
- Some members of the option can be omitted but their values will be
- automatically computed:
+ totally on the machine, 2 dies per socket, 2 modules per die, 2 cores per
+ module, 2 threads per core) for PC machines which support sockets/dies
+ /modules/cores/threads. Some members of the option can be omitted but
+ their values will be automatically computed:
::
- -smp 16,sockets=2,dies=2,cores=2,threads=2,maxcpus=16
+ -smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32
The following sub-option defines a CPU topology hierarchy (2 sockets
totally on the machine, 2 clusters per socket, 2 cores per cluster,
--
2.34.1
- [PATCH v8 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), (continued)
- [PATCH v8 08/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2024/01/31
- [PATCH v8 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/01/31
- [PATCH v8 09/21] i386/cpu: Introduce bitmap to cache available CPU topology levels, Zhao Liu, 2024/01/31
- [PATCH v8 11/21] i386/cpu: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2024/01/31
- [PATCH v8 12/21] i386: Introduce module level cpu topology to CPUX86State, Zhao Liu, 2024/01/31
- [PATCH v8 16/21] i386/cpu: Introduce module-id to X86CPU, Zhao Liu, 2024/01/31
- [PATCH v8 13/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2024/01/31
- [PATCH v8 15/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2024/01/31
- [PATCH v8 17/21] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2024/01/31
- [PATCH v8 14/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2024/01/31
- [PATCH v8 18/21] hw/i386/pc: Support smp.modules for x86 PC machine,
Zhao Liu <=
- [PATCH v8 19/21] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2024/01/31
- [PATCH v8 20/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2024/01/31
- [PATCH v8 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2024/01/31
- Re: [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU, Daniel P . Berrangé, 2024/01/31