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[PATCH rfcv1 07/23] intel_iommu: process PASID cache invalidation
From: |
Zhenzhong Duan |
Subject: |
[PATCH rfcv1 07/23] intel_iommu: process PASID cache invalidation |
Date: |
Mon, 15 Jan 2024 18:37:19 +0800 |
From: Yi Liu <yi.l.liu@intel.com>
This adds PASID cache invalidation handling. When guest updated
a pasid entry in scalable mode, guest software should issue a proper
PASID cache invalidation when caching-mode is exposed. This can happen
even when pasid is disabled as rid_pasid will still be used.
This only adds a basic framework for handling pasid cache invalidation.
Detailed handling will be added in subsequent patches.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
hw/i386/intel_iommu_internal.h | 12 ++++++++++
hw/i386/intel_iommu.c | 40 +++++++++++++++++++++++++++++-----
hw/i386/trace-events | 3 +++
3 files changed, 50 insertions(+), 5 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 6d881adf9b..10117e2f25 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -444,6 +444,18 @@ typedef union VTDInvDesc VTDInvDesc;
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
+#define VTD_INV_DESC_PASIDC_G (3ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID(val) (((val) >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PASIDC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
+#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000ffc0ULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL1 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL2 0xffffffffffffffffULL
+#define VTD_INV_DESC_PASIDC_RSVD_VAL3 0xffffffffffffffffULL
+
+#define VTD_INV_DESC_PASIDC_DSI (0ULL << 4)
+#define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4)
+#define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4)
+
/* Information about page-selective IOTLB invalidate */
struct VTDIOTLBPageInvInfo {
uint16_t domain_id;
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index c0973aaccb..effbeed8a3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2635,6 +2635,37 @@ static bool vtd_process_iotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
return true;
}
+static bool vtd_process_pasid_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ if ((inv_desc->val[0] & VTD_INV_DESC_PASIDC_RSVD_VAL0) ||
+ (inv_desc->val[1] & VTD_INV_DESC_PASIDC_RSVD_VAL1) ||
+ (inv_desc->val[2] & VTD_INV_DESC_PASIDC_RSVD_VAL2) ||
+ (inv_desc->val[3] & VTD_INV_DESC_PASIDC_RSVD_VAL3)) {
+ error_report_once("non-zero-field-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ switch (inv_desc->val[0] & VTD_INV_DESC_PASIDC_G) {
+ case VTD_INV_DESC_PASIDC_DSI:
+ break;
+
+ case VTD_INV_DESC_PASIDC_PASID_SI:
+ break;
+
+ case VTD_INV_DESC_PASIDC_GLOBAL:
+ break;
+
+ default:
+ error_report_once("invalid-inv-granu-in-pc_inv_desc hi: 0x%" PRIx64
+ " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]);
+ return false;
+ }
+
+ return true;
+}
+
static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -2736,12 +2767,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
- /*
- * TODO: the entity of below two cases will be implemented in future
series.
- * To make guest (which integrates scalable mode support patch set in
- * iommu driver) work, just return true is enough so far.
- */
case VTD_INV_DESC_PC:
+ trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]);
+ if (!vtd_process_pasid_desc(s, &inv_desc)) {
+ return false;
+ }
break;
case VTD_INV_DESC_PIOTLB:
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index 53c02d7ac8..e54799ee82 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d"
vtd_inv_qi_tail(uint16_t head) "write tail %d"
vtd_inv_qi_fetch(void) ""
vtd_context_cache_reset(void) ""
+vtd_pasid_cache_gsi(void) ""
+vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation domain
0x%"PRIx16
+vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC
invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32
vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present"
vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"
devfn %"PRIu8" not present"
vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t
domain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64"
domain 0x%"PRIx16
--
2.34.1
- [PATCH rfcv1 00/23] intel_iommu: Enable stage-1 translation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 02/23] backends/iommufd: add helpers for allocating user-managed HWPT, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 01/23] Update linux header to support nested hwpt alloc, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 03/23] backends/iommufd_device: introduce IOMMUFDDevice targeted interface, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 04/23] vfio: implement IOMMUFDDevice interface callbacks, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 05/23] intel_iommu: add a placeholder variable for scalable modern mode, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 06/23] intel_iommu: check and sync host IOMMU cap/ecap in scalable modern mode, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 07/23] intel_iommu: process PASID cache invalidation,
Zhenzhong Duan <=
- [PATCH rfcv1 08/23] intel_iommu: add PASID cache management infrastructure, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 09/23] vfio/iommufd_device: Add ioas_id in IOMMUFDDevice and pass to vIOMMU, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 10/23] intel_iommu: bind/unbind guest page table to host, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 11/23] intel_iommu: ERRATA_772415 workaround, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 12/23] intel_iommu: replay pasid binds after context cache invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 13/23] intel_iommu: process PASID-based iotlb invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 14/23] intel_iommu: propagate PASID-based iotlb invalidation to host, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 15/23] intel_iommu: process PASID-based Device-TLB invalidation, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 16/23] intel_iommu: rename slpte in iotlb_entry to pte, Zhenzhong Duan, 2024/01/15
- [PATCH rfcv1 17/23] intel_iommu: implement firt level translation, Zhenzhong Duan, 2024/01/15