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[PULL 14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64
From: |
Peter Maydell |
Subject: |
[PULL 14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64 |
Date: |
Thu, 11 Jan 2024 11:04:38 +0000 |
The TBFLAG_A64 TB flag bits go in flags2, which for AArch64 guests
we know is 64 bits. However at the moment we use FIELD_EX32() and
FIELD_DP32() to read and write these bits, which only works for
bits 0 to 31. Since we're about to add a flag that uses bit 32,
switch to FIELD_EX64() and FIELD_DP64() so that this will work.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
---
target/arm/cpu.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8da6bfda228..6dd0f642581 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3237,12 +3237,14 @@ FIELD(TBFLAG_A64, NAA, 30, 1)
FIELD(TBFLAG_A64, ATA0, 31, 1)
/*
- * Helpers for using the above.
+ * Helpers for using the above. Note that only the A64 accessors use
+ * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags
+ * word either is or might be 32 bits only.
*/
#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
(DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
#define DP_TBFLAG_A64(DST, WHICH, VAL) \
- (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
+ (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
#define DP_TBFLAG_A32(DST, WHICH, VAL) \
(DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
#define DP_TBFLAG_M32(DST, WHICH, VAL) \
@@ -3251,7 +3253,7 @@ FIELD(TBFLAG_A64, ATA0, 31, 1)
(DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
-#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH)
#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
--
2.34.1
- [PULL 00/41] target-arm queue, Peter Maydell, 2024/01/11
- [PULL 01/41] hw/arm: add cache controller for Freescale i.MX6, Peter Maydell, 2024/01/11
- [PULL 04/41] hw/intc/armv7m_nvic: add "num-prio-bits" property, Peter Maydell, 2024/01/11
- [PULL 07/41] hw/arm: Add missing QOM parent for v7-M SoCs, Peter Maydell, 2024/01/11
- [PULL 03/41] hw/arm: Add minimal support for the B-L475E-IOT01A board, Peter Maydell, 2024/01/11
- [PULL 05/41] hw/arm/armv7m: alias the NVIC "num-prio-bits" property, Peter Maydell, 2024/01/11
- [PULL 14/41] target/arm: Allow use of upper 32 bits of TBFLAG_A64,
Peter Maydell <=
- [PULL 41/41] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs, Peter Maydell, 2024/01/11
- [PULL 38/41] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers, Peter Maydell, 2024/01/11
- [PULL 02/41] hw/arm: Add minimal support for the STM32L4x5 SoC, Peter Maydell, 2024/01/11
- [PULL 06/41] hw/arm/socs: configure priority bits for existing SOCs, Peter Maydell, 2024/01/11
- [PULL 09/41] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers, Peter Maydell, 2024/01/11
- [PULL 08/41] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU, Peter Maydell, 2024/01/11