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[PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE}
From: |
Richard Henderson |
Subject: |
[PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE} |
Date: |
Thu, 11 Jan 2024 09:43:51 +1100 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231028194522.245170-12-richard.henderson@linaro.org>
[PMD: Split from bigger patch, part 2/2]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231108145244.72421-2-philmd@linaro.org>
---
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 29 ++++++++++++++++++++++++++++-
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 7bf42045a7..a43875cb09 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -125,7 +125,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_qemu_ldst_i128 0
-#define TCG_TARGET_HAS_tst 0
+#define TCG_TARGET_HAS_tst 1
#define TCG_TARGET_HAS_v64 use_neon_instructions
#define TCG_TARGET_HAS_v128 use_neon_instructions
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 66d71af8bf..0fc7273b16 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1194,7 +1194,27 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
static TCGCond tcg_out_cmp(TCGContext *s, TCGCond cond, TCGReg a,
TCGArg b, int b_const)
{
- tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const);
+ if (!is_tst_cond(cond)) {
+ tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, a, b, b_const);
+ return cond;
+ }
+
+ cond = tcg_tst_eqne_cond(cond);
+ if (b_const) {
+ int imm12 = encode_imm(b);
+
+ /*
+ * The compare constraints allow rIN, but TST does not support N.
+ * Be prepared to load the constant into a scratch register.
+ */
+ if (imm12 >= 0) {
+ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, a, imm12);
+ return cond;
+ }
+ tcg_out_movi32(s, COND_AL, TCG_REG_TMP, b);
+ b = TCG_REG_TMP;
+ }
+ tcg_out_dat_reg(s, COND_AL, ARITH_TST, 0, a, b, SHIFT_IMM_LSL(0));
return cond;
}
@@ -1225,6 +1245,13 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg
*args,
tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl);
return cond;
+ case TCG_COND_TSTEQ:
+ case TCG_COND_TSTNE:
+ /* Similar, but with TST instead of CMP. */
+ tcg_out_dat_rI(s, COND_AL, ARITH_TST, 0, ah, bh, const_bh);
+ tcg_out_dat_rI(s, COND_EQ, ARITH_TST, 0, al, bl, const_bl);
+ return tcg_tst_eqne_cond(cond);
+
case TCG_COND_LT:
case TCG_COND_GE:
/* We perform a double-word subtraction and examine the result.
--
2.34.1
- Re: [PATCH v3 15/38] target/s390x: Improve general case of disas_jcc, (continued)
[PATCH v3 15/38 1/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (1/5), Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 15/38 2/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (2/5), Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5), Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 15/38 4/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (4/5), Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 15/38 5/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (5/5), Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 15/38 6/6] target/s390x: Improve general case of disas_jcc, Philippe Mathieu-Daudé, 2024/01/19
[PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE},
Richard Henderson <=
[PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond, Richard Henderson, 2024/01/10
[PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX, Richard Henderson, 2024/01/10
[PATCH v3 20/38] tcg/arm: Factor tcg_out_cmp() out, Richard Henderson, 2024/01/10
[PATCH v3 22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov, Richard Henderson, 2024/01/10
[PATCH v3 24/38] tcg/i386: Support TCG_COND_TST{EQ,NE}, Richard Henderson, 2024/01/10
[PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel, Richard Henderson, 2024/01/10